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Publication search results
found 83 matches
- 2011
- Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
A hybrid algorithm for the optimization of area and delay in linear DSP transforms. VLSI-SoC 2011: 148-153 - Antonio Artés, José Luis Ayala, Ashoka Visweswara Sathanur, Jos Huisken, Francky Catthoor:
Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications. VLSI-SoC 2011: 136-141 - Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu:
Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC). VLSI-SoC 2011: 242-247 - Yiorgos I. Bontzios, Michael G. Dimopoulos, Alkis A. Hatzopoulos:
Prospects of 3D inductors on through silicon vias processes for 3D ICs. VLSI-SoC 2011: 90-93 - Marcel Veloso Campos, André Luís Fortunato, Carlos Alberto dos Reis Filho:
New 12-bit source-follower track-and-hold circuit suitable for high-speed applications. VLSI-SoC 2011: 82-85 - Fabio Cenni, Serge Scotti, Emmanuel Simeu:
SystemC AMS behavioral modeling of a CMOS video sensor. VLSI-SoC 2011: 380-385 - Yang Chai, Minghui Sun, Zhiyong Xiao, Yuan Li, Min Zhang, Philip C. H. Chan:
Towards future VLSI interconnects using aligned carbon nanotubes. VLSI-SoC 2011: 248-253 - Anupam Chattopadhyay, Zoltan Endre Rakosi:
Combinational logic synthesis for material implication. VLSI-SoC 2011: 200-203 - Huan Chen, João Marques-Silva:
Improvements to satisfiability-based boolean function bi-decomposition. VLSI-SoC 2011: 142-147 - Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Lima Kastensmidt, Gianluca Palermo, Cristina Silvano:
Two-levels of adaptive buffer for virtual channel router in NoCs. VLSI-SoC 2011: 302-307 - Nizar Dahir, Terrence S. T. Mak, Alex Yakovlev:
Communication centric on-chip power grid models for networks-on-chip. VLSI-SoC 2011: 180-183 - Charvi Dhoot, Vincent John Mooney, Shubhajit Roy Chowdhury, Lap-Pui Chau:
Fault tolerant design for low power hierarchical search motion estimation algorithms. VLSI-SoC 2011: 266-271 - Josef Dobes, David Cerný, Abhimanyu Yadav:
A more efficient arrangement of the sparse LU factorization for the large-scale circuit analysis. VLSI-SoC 2011: 416-421 - Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Agent-based on-chip network using efficient selection method. VLSI-SoC 2011: 284-289 - Felipe Frantz, Lioua Labrak, Ian O'Connor:
3D-IC floorplanning: Applying meta-optimization to improve performance. VLSI-SoC 2011: 404-409 - Franco Fummi, Davide Quaglia, Francesco Stefanni:
Communication-aware middleware-based design-space exploration for Networked Embedded Systems. VLSI-SoC 2011: 168-171 - J. Gerardo García-Sánchez, José M. de la Rosa:
Multirate hybrid continuous-time/discrete-time cascade 2-2 ΣΔ modulator for wideband telecom. VLSI-SoC 2011: 314-318 - Alberto Ghiribaldi, Daniele Ludovici, Michele Favalli, Davide Bertozzi:
System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic. VLSI-SoC 2011: 308-313 - Wenmin Hu, Zhonghai Lu, Axel Jantsch, Hengzhu Liu, Botao Zhang, Dongpei Liu:
Network-on-Chip multicasting with low latency path setup. VLSI-SoC 2011: 290-295 - Tzu-Chi Huang, Yao-Yi Yang, Yu-Huei Lee, Ming-Jhe Du, Shih-Hsien Cheng, Ke-Horng Chen:
A battery-free energy harvesting system with the switch capacitor sampler (SCS) technique for high power factor in smart meter applications. VLSI-SoC 2011: 359-362 - Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi:
An easily testable routing architecture of FPGA. VLSI-SoC 2011: 106-109 - Keisuke Inoue, Mineo Kaneko:
Early planning for RT-level delay insertion during clock skew-aware register binding. VLSI-SoC 2011: 154-159 - Hong-Yuan Jheng, Yen-Hsiang Chen, Shanq-Jang Ruan, Ziming Qi:
FPGA implementation of high sampling rate in-car non-stationary noise cancellation based on adaptive Wiener filter. VLSI-SoC 2011: 114-117 - Jianfei Jiang, Xu Wang, Wei-Guang Sheng, Wei-Feng He, Zhi-Gang Mao:
A clock-less transceiver for global interconnect. VLSI-SoC 2011: 184-187 - Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao:
A 230mV 8-bit sub-threshold microprocessor for wireless sensor network. VLSI-SoC 2011: 126-129 - Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao:
Robust design of sub-threshold flip-flop cells for wireless sensor network. VLSI-SoC 2011: 440-443 - Naifeng Jing, Weifeng He, Zhigang Mao:
A general statistical estimation for application mapping in Network-on-Chip. VLSI-SoC 2011: 172-175 - Tso-Bing Juang, Hsin-Hao Peng, Chao-Tsung Kuo:
Area-efficient 3-input decimal adders using simplified carry and sum vectors. VLSI-SoC 2011: 25-30 - Asim Khan, Kyungsu Kang, Chong-Min Kyung:
Exploiting maximum throughput in 3D multicore architectures with stacked NUCA cache. VLSI-SoC 2011: 130-135 - Wing-Hung Ki, Yan Lu, Feng Su, Chi-Ying Tsui:
Design and analysis of on-chip charge pumps for micro-power energy harvesting applications. VLSI-SoC 2011: 374-379
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