• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 37 matches

• 2012
• 
  Ashfaq Ahmed, Muhammad Usman Shahid, Ata ur Rehman:
  Point DCT VLSI Architecture for Emerging HEVC Standard. VLSI Design 2012: 752024:1-752024:13 (2012)
• 
  Maher Assaad, Mohammed H. Alser:
  Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture. VLSI Design 2012: 546212:1-546212:7 (2012)
• 
  Muhammad Awais, Carlo Condo:
  Flexible LDPC Decoder Architectures. VLSI Design 2012: 730835:1-730835:16 (2012)
• 
  P. Balasubramanian, David A. Edwards, William B. Toms:
  Redundant Logic Insertion and Latency Reduction in Self-Timed Adders. VLSI Design 2012: 575389:1-575389:13 (2012)
• 
  Massimo Bariani, Paolo Lambruschini, Marco Raggio:
  An Efficient Multi-Core SIMD Implementation for H.264/AVC Encoder. VLSI Design 2012: 413747:1-413747:14 (2012)
• 
  Emanuele Cannella, Onur Derin, Paolo Meloni, Giuseppe Tuveri, Todor P. Stefanov:
  Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks. VLSI Design 2012: 987209:1-987209:17 (2012)
• 
  Guilherme Corrêa, Daniel Palomino, Cláudio Machado Diniz, Sergio Bampi, Luciano Volcan Agostini:
  Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder. VLSI Design 2012: 748019:1-748019:20 (2012)
• 
  Dionysios Diamantopoulos, Kostas Siozios, Sotirios Xydis, Dimitrios Soudris:
  A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems. VLSI Design 2012: 784945:1-784945:15 (2012)
• 
  Chia-Hao Fang, I-tao Lung, Chih-Peng Fan:
  Absolute Difference and Low-Power Bus Encoding Method for LCD Digital Display Interfaces. VLSI Design 2012: 657897:1-657897:6 (2012)
• 
  Christina Gimmler-Dumont, Frank Kienle, Bin Wu, Guido Masera:
  A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection. VLSI Design 2012: 826350:1-826350:14 (2012)
• 
  Khaled Grati, Nadia Khouja, Bertrand Le Gal, Adel Ghazel:
  Power Consumption Models for Decimation FIR Filters in Multistandard Receivers. VLSI Design 2012: 870546:1-870546:15 (2012)
• 
  Sheng-Chieh Huang, Hui-Min Wang, Wei-Yu Chen:
  A ±6 ms-Accuracy, 0.68 mm², and 2.21 μW QRS Detection ASIC. VLSI Design 2012: 809393:1-809393:13 (2012)
• 
  Yahya Jan, Lech Józwiak:
  Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors. VLSI Design 2012: 794753:1-794753:20 (2012)
• 
  S. Jayanthy, M. C. Bhuvaneswari, Keesarapalli Sujitha:
  Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm. VLSI Design 2012: 745861:1-745861:10 (2012)
• 
  Khaled Jerbi, Mickaël Raulet, Olivier Déforges, Mohamed Abid:
  Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs. VLSI Design 2012: 298396:1-298396:14 (2012)
• 
  Maher Jridi, Ayman Alfalou, Pramod Kumar Meher:
  Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression. VLSI Design 2012: 209208:1-209208:12 (2012)
• 
  Maurizio Martina, Muhammad Shafique, Andrey Norkin:
  VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards. VLSI Design 2012: 102585:1-102585:3 (2012)
• 
  Muhammad Martuza, Khan A. Wahid:
  Low Cost Design of a Hybrid Architecture of Integer Inverse DCT for H.264, VC-1, AVS, and HEVC. VLSI Design 2012: 242989:1-242989:10 (2012)
• 
  Guido Masera, Amer Baghdadi, Frank Kienle, Christophe Moy:
  Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation. VLSI Design 2012: 549768:1-549768:2 (2012)
• 
  Paolo Meloni, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, Menno Lindwer:
  Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper. VLSI Design 2012: 580584:1-580584:16 (2012)
• 
  Joyjit Mukhopadhyay, Soumya Pandit:
  Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics. VLSI Design 2012: 505983:1-505983:13 (2012)
• 
  Van Tam Nguyen, Frederic Villain, Yann Le Guillou:
  Cognitive Radio RF: Overview and Challenges. VLSI Design 2012: 716476:1-716476:13 (2012)
• 
  Leonardo Palacios-Luengas, Gonzalo Isaac Duchen-Sánchez, José Luis Aragón-Vera, Ruben Vázquez-Medina:
  Digital Noise Generator Design Using Inverted 1D Tent Chaotic Map. VLSI Design 2012: 849120:1-849120:10 (2012)
• 
  Min Pan, Yue Xu, Yanheng Zhang, Chris Chu:
  FastRoute: An Efficient and High-Quality Global Router. VLSI Design 2012: 608362:1-608362:18 (2012)
• 
  Roberta Piscitelli, Andy D. Pimentel:
  A Signature-Based Power Model for MPSoC on FPGA. VLSI Design 2012: 196984:1-196984:13 (2012)
• 
  Logan M. Rakai, Amin Farshidi, Laleh Behjat, David T. Westwick:
  A New Length-Based Algebraic Multigrid Clustering Algorithm. VLSI Design 2012: 395260:1-395260:14 (2012)
• 
  D. S. Harish Ram, M. C. Bhuvaneswari, Shanthi S. Prabhu:
  A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths. VLSI Design 2012: 273276:1-273276:12 (2012)
• 
  Sergio Saponara, Luca Fanucci:
  Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing. VLSI Design 2012: 450302:1-450302:17 (2012)
• 
  Philipp Schläfer, Christian Weis, Norbert Wehn, Matthias Alles:
  Design Space of Flexible Multigigabit LDPC Decoders. VLSI Design 2012: 942893:1-942893:10 (2012)
• 
  Shiwani Singh, Tripti Sharma, K. G. Sharma, B. P. Singh:
  9T Full Adder Design in Subthreshold Region. VLSI Design 2012: 248347:1-248347:5 (2012)

skipping 7 more matches