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Alessandro Cilardo
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Publications
- 2015
- [j16]Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo:
Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects. ACM Trans. Embed. Comput. Syst. 14(3): 57:1-57:24 (2015) - [c30]Alessandro Cilardo, Luca Gallo:
Interplay of loop unrolling and multidimensional memory partitioning in HLS. DATE 2015: 163-168 - 2014
- [j14]Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo, Nicola Mazzocca:
Automated design space exploration for FPGA-based heterogeneous interconnects. Des. Autom. Embed. Syst. 18(3-4): 157-170 (2014) - [j11]Alessandro Cilardo, Luca Gallo:
Improving Multibank Memory Access Parallelism with Lattice-Based Partitioning. ACM Trans. Archit. Code Optim. 11(4): 45:1-45:25 (2014) - [c24]Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo:
Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems. DATE 2014: 1-4 - [c23]Alessandro Cilardo, Luca Gallo:
Generating On-Chip Heterogeneous Systems from High-Level Parallel Code. DSD 2014: 161-168 - [c22]Luca Gallo, Alessandro Cilardo, David B. Thomas, Samuel Bayliss, George A. Constantinides:
Area implications of memory partitioning for high-level synthesis on FPGAs. FPL 2014: 1-4 - 2013
- [j9]Alessandro Cilardo, Luca Gallo, Nicola Mazzocca:
Design space exploration for high-level synthesis of multi-threaded applications. J. Syst. Archit. 59(10-D): 1171-1183 (2013) - [c21]Alessandro Cilardo, Luca Gallo, Antonino Mazzeo, Nicola Mazzocca:
Efficient and scalable OpenMP-based system-level design. DATE 2013: 988-991 - [c20]Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo:
Automated synthesis of FPGA-based heterogeneous interconnect topologies. FPL 2013: 1-8
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