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ORCID26th ARCS 2013: Prague, Czech Republic
- Hana Kubátová, Christian Hochberger, Martin Danek, Bernhard Sick:
Architecture of Computing Systems - ARCS 2013 - 26th International Conference, Prague, Czech Republic, February 19-22, 2013. Proceedings. Lecture Notes in Computer Science 7767, Springer 2013, ISBN 978-3-642-36423-5 - JongBeom Lim, Kwang-Sik Chung
, Joon-Min Gil, Taeweon Suh, Heon-Chang Yu:
An Unstructured Termination Detection Algorithm Using Gossip in Cloud Computing Environments. 1-12 - Boris Motruk, Jonas Diemer, Rainer Buchty, Mladen Berekovic:
Power Monitoring for Mixed-Criticality on a Many-Core Platform. 13-24 - Yang Xu, Bo Wang, Rafael Rosales, Ralph Hasholzner, Jürgen Teich:
On Confident Task-Accurate Performance Estimation. 25-37 - Maciej Zbierski:
Iwazaru: The Byzantine Sequencer. 38-49 - Simone Corbetta, William Fornaciari:
Exploiting Thermal Coupling Information in MPSoC Dynamic Thermal Management. 50-61 - Jared Sherman, Krishna M. Kavi, Brandon Potter, Mike Ignatowski:
A Multi-core Memory Organization for 3-D DRAM as Main Memory. 62-73 - Pascal Schleuniger, Anders Kusk, Jørgen Dall, Sven Karlsson:
Synthetic Aperture Radar Data Processing on an FPGA Multi-core System. 74-85 - Mageda Sharafeddine, Haitham Akkary, Doug Carmean:
Virtual Register Renaming. 86-97 - Josef Strnadel:
Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates. 98-109 - Arnau Prat-Pérez, David Dominguez-Sal, Josep Lluís Larriba-Pey, Pedro Trancoso:
Producer-Consumer: The Programming Model for Future Many-Core Processors. 110-121 - Benjamin Betting, Julius von Rosen, Lars Hedrich, Uwe Brinkschulte:
A Highly Dependable Self-adaptive Mixed-Signal Multi-core System-on-Chip. 122-133 - Ahmad Lashgar, Amirali Baniasadi, Ahmad Khonsari:
Inter-warp Instruction Temporal Locality in Deep-Multithreaded GPUs. 134-146 - Muhammad Nadeem, HeeJong Park, Zhenmin Li, Morteza Biglari-Abhari, Zoran Salcic:
GALS-CMP: Chip-Multiprocessor for GALS Embedded Systems. 147-158 - Tobias Ziermann, Zoran Salcic, Jürgen Teich:
HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN). 159-170 - Fabian Nowak, Ingo Besenfelder, Wolfgang Karl, Mareike Schmidtobreick, Vincent Heuveline:
A Data-Driven Approach for Executing the CG Method on Reconfigurable High-Performance Systems. 171-182 - Rico Backasch, Christian Hochberger:
Custom Reconfigurable Architecture Based on Virtex 5 Lookup Tables. 183-194 - Shiao-Li Tsao, Cheng-Kun Yu, Yi-Hsin Chang:
Profiling Energy Consumption of I/O Functions in Embedded Applications. 195-206 - Tripti S. Warrier, B. Anupama, Madhu Mutyam:
An Application-Aware Cache Replacement Policy for Last-Level Caches. 207-219 - Epifanio Gaona-Ramírez, José L. Abellán, Manuel E. Acacio, Juan Fernández:
Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memory. 220-231 - Jan Hartmann, Walter Stechele, Erik Maehle:
Self-adaptation for Mobile Robot Algorithms Using Organic Computing Principles. 232-243 - Christian Herber, Andre Oliver Richter, Holm Rauchfuss, Andreas Herkersdorf:
Self-virtualized CAN Controller for Multi-core Processors in Real-Time Applications. 244-255 - Alexandra Ferrerón-Labari, Marta Ortín-Obón, Darío Suárez Gracia, Jesús Alastruey-Benedé, Víctor Viñals Yúfera:
Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors. 256-267 - Josef Hlavác, Róbert Lórencz:
Arithmetic Unit for Computations in GF(p) with the Left-Shifting Multiplicative Inverse Algorithm. 268-279 - Stefan Wallentowitz, Thomas Wild, Andreas Herkersdorf:
HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation. 280-291 - Marcin Pietron, Maciej Wielgosz, Dominik Zurek, Ernest Jamro, Kazimierz Wiatr:
Comparison of GPU and FPGA Implementation of SVM Algorithm for Fast Image Segmentation. 292-302 - Christian Beckhoff, Dirk Koch, Jim Tørresen:
Automatic Floorplanning and Interface Synthesis of Island Style Reconfigurable Systems with GoAhead. 303-316 - Catalin Bogdan Ciobanu, Georgi Nedeltchev Gaydadjiev:
Separable 2D Convolution with Polymorphic Register Files. 317-328 - Tomás Zahradnický, Róbert Lórencz:
Architecture of a Parallel MOSFET Parameter Extraction System. 329-340 - Roman Bourgade, Christine Rochange, Pascal Sainrat:
Predictable Two-Level Bus Arbitration for Heterogeneous Task Sets. 341-351
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