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2020 – today
- 2024
[c134]Lukas Frickenstein, Pierpaolo Morì, Shambhavi Balamuthu Sampath, Moritz Thoma, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Christian Unger, Claudio Passerone, Walter Stechele:
Pruning as a Binarization Technique. CVPR Workshops 2024: 2131-2140- [c133]Pierpaolo Morì, Moritz Thoma, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone:
MATAR: Multi-Quantization-Aware Training for Accurate and Fast Hardware Retargeting. DATE 2024: 1-6 - [c132]Pierpaolo Morì, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Moritz Thoma, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Christian Unger, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone:
Wino Vidi Vici: Conquering Numerical Instability of 8-bit Winograd Convolution for Accurate Inference Acceleration on Edge. WACV 2024: 53-62 - 2023
- [j18]Zhongliang Jiang
, Xuesong Li, Chenyu Zhang, Yuan Bi, Walter Stechele, Nassir Navab:
Skeleton Graph-Based Ultrasound-CT Non-Rigid Registration. IEEE Robotics Autom. Lett. 8(8): 4394-4401 (2023) - [c131]Pierpaolo Morì, Shambhavi Balamuthu Sampath, Lukas Frickenstein, Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Walter Stechele, Claudio Passerone:
WinoTrain: Winograd-Aware Training for Accurate Full 8-bit Convolution Acceleration. DAC 2023: 1-6 - [c130]Lukas Frickenstein, Shambhavi Balamuthu Sampath, Pierpaolo Morì, Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Christian Unger, Claudio Passerone, Walter Stechele:
Adversarial Robustness of Multi-bit Convolutional Neural Networks. IntelliSys (3) 2023: 157-174 - [c129]Simon Friedrich, Shambhavi Balamuthu Sampath, Robert Wittig, Manoj Rohit Vemparala, Nael Fasfous, Emil Matús, Walter Stechele, Gerhard P. Fettweis:
Lightweight Instruction Set for Flexible Dilated Convolutions and Mixed-Precision Operands. ISQED 2023: 1-8 - [i13]Zhongliang Jiang, Xuesong Li, Chenyu Zhang, Yuan Bi, Walter Stechele, Nassir Navab:
Skeleton Graph-based Ultrasound-CT Non-rigid Registration. CoRR abs/2305.08228 (2023) - [i12]Jonas Kantic, Fabian C. Legl, Walter Stechele, Jakob Hermann:
ReLiCADA - Reservoir Computing using Linear Cellular Automata Design Algorithm. CoRR abs/2308.11522 (2023) - 2022
- [j17]Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Emanuele Valpreda, Manfredi Camalleri, Qi Zhao, Christian Unger, Naveen Shankar Nagaraja, Maurizio Martina, Walter Stechele:
HW-Flow: A Multi-Abstraction Level HW-CNN Codesign Pruning Methodology. Leibniz Trans. Embed. Syst. 8(1): 03:1-03:30 (2022) - [j16]Zhongliang Jiang, Zhenyu Li, Matthias Grimm, Mingchuan Zhou, Marco Esposito, Wolfgang Wein, Walter Stechele, Thomas Wendler, Nassir Navab:
Autonomous Robotic Screening of Tubular Structures Based Only on Real-Time Ultrasound Imaging Feedback. IEEE Trans. Ind. Electron. 69(7): 7064-7075 (2022) - [c128]Pierpaolo Morì, Manoj Rohit Vemparala, Nael Fasfous, Saptarshi Mitra, Sreetama Sarkar, Alexander Frickenstein, Lukas Frickenstein, Domenik Helms, Naveen Shankar Nagaraja, Walter Stechele, Claudio Passerone:
Accelerating and pruning CNNs for semantic segmentation on FPGA. DAC 2022: 145-150 - [c127]Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Driton Salihu, Julian Höfer, Anmol Singh, Naveen Shankar Nagaraja, Hans-Jörg Vögel, Nguyen Anh Vu Doan, Maurizio Martina, Jürgen Becker, Walter Stechele:
AnaCoNGA: Analytical HW-CNN Co-Design Using Nested Genetic Algorithms. DATE 2022: 238-243 - [c126]Nael Fasfous, Lukas Frickenstein, Michael Neumeier, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Maurizio Martina, Walter Stechele:
Mind the Scaling Factors: Resilience Analysis of Quantized Adversarially Robust CNNs. DATE 2022: 706-711 - [c125]Korbinian Weikl, Damien Schroeder, Walter Stechele:
Potentials of combined visible light and near infrared imaging for driving automation. Autonomous Vehicles and Machines 2022: 1-5 - [c124]Manu Manuel, Benjamin Hien, Simon Conrady, Arne Kreddig, Nguyen Anh Vu Doan, Walter Stechele:
Region of interest based non-dominated sorting genetic algorithm-II: an invite and conquer approach. GECCO 2022: 556-564 - [c123]Furkan Kaynar, Peter Geißler, Laurent Demaret, Tamara Seybold, Walter Stechele:
Non-iterative Blind Deblurring of Digital Microscope Images with Spatially Varying Blur. MIUA 2022: 703-718 - 2021
- [j15]Manu Manuel, Arne Kreddig, Simon Conrady, Nguyen Anh Vu Doan, Walter Stechele:
Region of Interest-Based Parameter Optimization for Approximate Image Processing on FPGAs. Int. J. Netw. Comput. 11(2): 438-462 (2021) - [j14]Simon Conrady, Arne Kreddig, Manu Manuel, Nguyen Anh Vu Doan, Walter Stechele:
Model-Based Design Space Exploration for FPGA-based Image Processing Applications Employing Parameterizable Approximations. Microprocess. Microsystems 87: 104386 (2021) - [j13]Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Driton Salihu, Nguyen Anh Vu Doan, Christian Unger, Naveen Shankar Nagaraja, Maurizio Martina, Walter Stechele:
HW-FlowQ: A Multi-Abstraction Level HW-CNN Co-design Quantization Methodology. ACM Trans. Embed. Comput. Syst. 20(5s): 66:1-66:25 (2021) - [c122]Manoj Rohit Vemparala, Nael Fasfous, Lukas Frickenstein, Alexander Frickenstein, Anmol Singh, Driton Salihu, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele:
Hardware-Aware Mixed-Precision Neural Networks using In-Train Quantization. BMVC 2021: 60 - [c121]Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Sreetama Sarkar, Qi Zhao, Sabine Kuhn, Lukas Frickenstein, Anmol Singh, Christian Unger, Naveen Shankar Nagaraja, Christian Wressnegger, Walter Stechele:
Adversarial Robust Model Compression Using In-Train Pruning. CVPR Workshops 2021: 66-75 - [c120]Arne Kreddig, Simon Conrady, Manu Manuel, Walter Stechele:
A Framework for Hardware-Accelerated Design Space Exploration for Approximate Computing on FPGA. DSD 2021: 1-8 - [c119]Korbinian Weikl, Damien Schroeder, Daniel Blau, Zhenyi Liu, Walter Stechele:
End-to-End Imaging System Optimization for Computer Vision in Driving Automation. Autonomous Vehicles and Machines 2021: 1-7 - [c118]Gábor Balázs, Mateusz Chmurski, Walter Stechele, Mariusz Zubert:
Sensor Fusion Neural Networks for Gesture Recognition on Low-power Edge Devices. ICAART (2) 2021: 141-150 - [c117]Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Mohamed Badawy, Felix Hundhausen, Julian Höfer, Naveen Shankar Nagaraja, Christian Unger, Hans-Jörg Vögel, Jürgen Becker, Tamim Asfour, Walter Stechele:
Binary-LoRAX: Low-Latency Runtime Adaptable XNOR Classifier for Semi-Autonomous Grasping with Prosthetic Hands. ICRA 2021: 13430-13437 - [c116]Manoj Rohit Vemparala, Alexander Frickenstein, Nael Fasfous, Lukas Frickenstein, Qi Zhao, Sabine Kuhn, Daniel Ehrhardt, Yuankai Wu, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele:
BreakingBED: Breaking Binary and Efficient Deep Neural Networks by Adversarial Attacks. IntelliSys (1) 2021: 148-167 - [c115]Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Lukas Frickenstein, Mohamed Badawy, Walter Stechele:
BinaryCoP: Binary Neural Network-based COVID-19 Face-Mask Wear and Positioning Predictor on Edge Devices. IPDPS Workshops 2021: 108-115 - [c114]Manoj Rohit Vemparala, Anmol Singh, Ahmed Mzid, Nael Fasfous, Alexander Frickenstein, Florian Mirus, Hans-Jörg Vögel, Naveen Shankar Nagaraja, Walter Stechele:
Pruning CNNs for LiDAR-based Perception in Resource Constrained Environments. IV Workshops 2021: 228-235 - [c113]Ee Heng Chen, Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Ahmed Mzid, Naveen Shankar Nagaraja, Jöran Zeisler, Walter Stechele:
Investigating Binary Neural Networks for Traffic Sign Detection and Recognition. IV 2021: 1400-1405 - [i11]Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Mhd Ali Moraly, Aquib Jamal, Lukas Frickenstein, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele:
L2PF - Learning to Prune Faster. CoRR abs/2101.02663 (2021) - [i10]Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Lukas Frickenstein, Walter Stechele:
BinaryCoP: Binary Neural Network-based COVID-19 Face-Mask Wear and Positioning Predictor on Edge Devices. CoRR abs/2102.03456 (2021) - [i9]Manoj Rohit Vemparala, Alexander Frickenstein, Nael Fasfous, Lukas Frickenstein, Qi Zhao, Sabine Kuhn, Daniel Ehrhardt, Yuankai Wu, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele:
BreakingBED - Breaking Binary and Efficient Deep Neural Networks by Adversarial Attacks. CoRR abs/2103.08031 (2021) - 2020
- [c112]Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Mhd Ali Moraly, Aquib Jamal, Lukas Frickenstein, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele:
L2PF - Learning to Prune Faster. CVIP (3) 2020: 249-261 - [c111]Alexander Frickenstein, Manoj Rohit Vemparala, Nael Fasfous, Laura Hauenschild, Naveen Shankar Nagaraja, Christian Unger, Walter Stechele:
ALF: Autoencoder-based Low-rank Filter-sharing for Efficient Convolutional Neural Networks. DAC 2020: 1-6 - [c110]Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele:
OrthrusPE: Runtime Reconfigurable Processing Elements for Binary Neural Networks. DATE 2020: 1662-1667 - [c109]Nguyen Anh Vu Doan, Manu Manuel, Simon Conrady, Arne Kreddig, Walter Stechele:
Parameter Optimization of Approximate Image Processing Algorithms in FPGAs. CANDAR (Workshops) 2020: 74-80 - [c108]Gábor Balázs, Walter Stechele:
Neural Architecture Search for Automotive Grid Fusion Networks Under Embedded Hardware Constraints. ICMLA 2020: 79-86 - [c107]Alexander Frickenstein, Manoj Rohit Vemparala, Jakob Mayr, Naveen Shankar Nagaraja, Christian Unger, Federico Tombari, Walter Stechele:
Binary DAD-Net: Binarized Driveable Area Detection Network for Autonomous Driving. ICRA 2020: 2295-2301 - [c106]Korbinian Weikl, Damien Schroeder, Walter Stechele:
Optimization of automotive color filter arrays for traffic light color separation. CIC 2020: 288-292 - [c105]Manu Manuel, Arne Kreddig, Simon Conrady, Nguyen Anh Vu Doan, Walter Stechele:
Model-Based Design Space Exploration for Approximate Image Processing on FPGA. NorCAS 2020: 1-7 - [i8]Alexander Frickenstein, Manoj Rohit Vemparala, Jakob Mayr, Naveen Shankar Nagaraja, Christian Unger, Federico Tombari, Walter Stechele:
Binary DAD-Net: Binarized Driveable Area Detection Network for Autonomous Driving. CoRR abs/2006.08178 (2020) - [i7]Alexander Frickenstein, Manoj Rohit Vemparala, Nael Fasfous, Laura Hauenschild, Naveen Shankar Nagaraja, Christian Unger, Walter Stechele:
ALF: Autoencoder-based Low-rank Filter-sharing for Efficient Convolutional Neural Networks. CoRR abs/2007.13384 (2020) - [i6]Zhongliang Jiang, Zhenyu Li, Matthias Grimm, Mingchuan Zhou, Marco Esposito, Wolfgang Wein, Walter Stechele, Thomas Wendler, Nassir Navab:
Autonomous Robotic Screening of Tubular Structures based only on Real-Time Ultrasound Imaging Feedback. CoRR abs/2011.00099 (2020)
2010 – 2019
- 2019
- [c104]Dirk Gabriel, Walter Stechele, Stefan Wildermann:
Resource-Aware Parameter Tuning for Real-Time Applications. ARCS 2019: 45-55 - [c103]Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele:
An Efficient FPGA Accelerator Design for Optimized CNNs Using OpenCL. ARCS 2019: 236-249 - [c102]Alexander Frickenstein, Christian Unger, Walter Stechele:
Resource-Aware Optimization of DNNs for Embedded Applications. CRV 2019: 17-24 - [c101]Alexander Frickenstein, Manoj Rohit Vemparala, Christian Unger, Fatih Ayar, Walter Stechele:
DSC: Dense-Sparse Convolution for Vectorized Inference of Convolutional Neural Networks. CVPR Workshops 2019: 1353-1360 - [c100]Simon Conrady, Manu Manuel, Arne Kreddig, Walter Stechele:
LCS-based automatic configuration of approximate computing parameters for FPGA system designs. GECCO (Companion) 2019: 1271-1279 - [c99]Gábor Balázs, Walter Stechele:
Deep Grid Fusion of Feature-Level Sensor Data with Convolutional Neural Networks. ICCVE 2019: 1-6 - [c98]Zhuangyi Jiang, Pengfei Xia, Kai Huang, Walter Stechele, Guang Chen, Zhenshan Bing, Alois C. Knoll:
Mixed Frame-/Event-Driven Fast Pedestrian Detection. ICRA 2019: 8332-8338 - 2018
- [c97]Sebastian Vogel, Mengyu Liang, Andre Guntoro, Walter Stechele, Gerd Ascheid:
Efficient hardware acceleration of CNNs using logarithmic data representation with arbitrary log-base. ICCAD 2018: 9 - 2017
- [j12]Biao Hu, Uzair Sharif, Rajat Koner, Guang Chen, Kai Huang, Feihu Zhang, Walter Stechele, Alois C. Knoll:
Random Finite Set Based Bayesian Filtering with OpenCL in a Heterogeneous Platform. Sensors 17(4): 843 (2017) - [c96]Stefan Tabel, Korbinian Weikl, Walter Stechele:
Hardware-accelerated CCD readout smear correction for Fast Solar Polarimeter. ASAP 2017: 67-74 - [c95]Gereon Hinz, Guang Chen, Muhammad Aafaque, Florian Röhrbein, Jörg Conradt, Zhenshan Bing, Zhongnan Qu, Walter Stechele, Alois C. Knoll:
Online Multi-object Tracking-by-Clustering for Intelligent Transportation System with Neuromorphic Vision Sensor. KI 2017: 142-154 - 2016
- [j11]Haifa Ben Salem, Thyagaraju Damarla, Kishan Sudusinghe, Walter Stechele, Shuvra S. Bhattacharyya:
Adaptive tracking of people and vehicles using mobile platforms. EURASIP J. Adv. Signal Process. 2016: 65 (2016) - [j10]Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner, Andreas Zwinkau:
Invasive computing for timing-predictable stream processing on MPSoCs. it Inf. Technol. 58(6): 267-280 (2016) - [c94]Kyunghun Lee, Haifa Ben Salem, Thyagaraju Damarla, Walter Stechele, Shuvra S. Bhattacharyya:
Prototyping real-time tracking systems on mobile devices. Conf. Computing Frontiers 2016: 301-308 - [c93]Walter Stechele, Tomasz Kryjak, Lionel Lacassagne, Dominique Houzet, Martin Danek:
Special session 1 automotive parallel computing challenges - architectures, applications and tricks. DASIP 2016: 161 - [c92]David May, Walter Stechele:
Voltage over-scaling in sequential circuits for approximate computing. DTIS 2016: 1-6 - [c91]Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
Preface. FPL 2016: 1 - [c90]Erol Koser, Korbinian Berthold, Ravi Kumar Pujari, Walter Stechele:
A Chip-level Redundant Threading (CRT) scheme for shared-memory protection. HPCS 2016: 116-124 - [c89]Erol Koser, Walter Stechele:
Tackling long duration transients in sequential logic. IOLTS 2016: 137-142 - [c88]Erol Koser, Sebastian Krosche, Walter Stechele:
Integrated Soft Error Resilience and Self-Test. VLSI-SoC 2016: 1-6 - [e3]Cristina Silvano, Walter Stechele, Stephan Wong, Jerónimo Castrillón, Michael Hübner, Amir Hossein Ashouri:
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, Automation And Test In Europe (DATE 2016), Dresden, Germany, March 18th, 2016. CEUR Workshop Proceedings 1643, CEUR-WS.org 2016 [contents] - [e2]Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016. IEEE 2016, ISBN 978-2-8399-1844-2 [contents] - 2015
- [j9]Jan Frost, Walter Stechele, Erik Maehle:
Self-reconfigurable control architecture for complex mobile robots. it Inf. Technol. 57(2): 122-129 (2015) - [j8]Johny Paul, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Manfred Kröhnert, Daniel Lohmann, Walter Stechele, Tamim Asfour, Wolfgang Schröder-Preikschat:
Self-adaptive corner detection on MPSoC through resource-aware programming. J. Syst. Archit. 61(10): 520-530 (2015) - [j7]Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
Resource-awareness on heterogeneous MPSoCs for image processing. J. Syst. Archit. 61(10): 668-680 (2015) - [c87]Raphael Polig, Heiner Giefers, Walter Stechele:
A soft-core processor array for relational operators. ASAP 2015: 17-24 - [c86]Erol Koser, Felix Miller, Walter Stechele:
Matching Detection and Correction Schemes for Soft Error Handling in Sequential Logic. DSD 2015: 706-713 - [c85]Johny Paul, Walter Stechele:
Predictability of image processing algorithms on heterogeneous MPSoC. ESTIMedia 2015: 1-2 - [c84]David May, Walter Stechele:
Design of fine-grained sequential approximate circuits using probability-aware fault emulation. ISLPED 2015: 73-78 - [c83]Tamara Seybold, Mathias Plichta, Walter Stechele:
Improving wavelet denoising based on an in-depth analysis of the camera color processing. Real-Time Image and Video Processing 2015: 94000Q - [c82]Walter Stechele:
Protecting FPGA-based automotive systems against soft errors through reduced precision redundancy. SIES 2015: 170-173 - 2014
- [j6]Tamara Seybold, Marion Knopp, Christian Keimel, Walter Stechele:
Beyond Standard Noise Models: Evaluating Denoising Algorithms with Respect to Realistic Camera Noise. Int. J. Semantic Comput. 8(2): 145-168 (2014) - [c81]Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour:
Improving Efficiency of Embedded Multi-core Platforms with Scratchpad Memories. ARCS Workshops 2014: 1-8 - [c80]Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat:
Resource-Aware Harris Corner Detection Based on Adaptive Pruning. ARCS 2014: 1-12 - [c79]Johny Paul, Walter Stechele, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert, Tamim Asfour:
Self-adaptive harris corner detector on heterogeneous many-core processor. DASIP 2014: 1-8 - [c78]Tamara Seybold, Özlem Cakmak, Christian Keimel, Walter Stechele:
Noise characteristics of a single sensor camera in digital color image processing. CIC 2014: 53-58 - [c77]Michael Frischke, Andreas J. Rohatschek, Walter Stechele:
Towards low-cost fault detection strategy of FPGA configuration memory in real-time systems. IOLTS 2014: 81-86 - [c76]David May, Walter Stechele:
Improving the significance of probabilistic circuit fault emulations. IOLTS 2014: 128-133 - [c75]Tamara Seybold, Florian Kuhn, Julian Habigt, Mark Hartenstein, Walter Stechele:
Automatic denoising parameter estimation using gradient histograms. VCIP 2014: 358-361 - [e1]Walter Stechele, Thomas Wild:
ARCS 2014 - 27th International Conference on Architecture of Computing Systems, Workshop Proceedings, February 25-28, 2014, Luebeck, Germany, University of Luebeck, Institute of Computer Engineering. VDE Verlag / IEEE Xplore 2014, ISBN 978-3-8007-3579-2 [contents] - [i5]Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour:
Resource-Aware Programming for Robotic Vision. CoRR abs/1405.2908 (2014) - [i4]Manfred Kröhnert, Nikolaus Vahrenkamp, Johny Paul, Walter Stechele, Tamim Asfour:
Resource Prediction for Humanoid Robots. CoRR abs/1405.2911 (2014) - 2013
- [j5]Johny Paul, Andreas Laika, Christopher Claus, Walter Stechele, Adam El Sayed Auf, Erik Maehle:
Real-time motion detection based on SW/HW-codesign for walking rescue robots. J. Real Time Image Process. 8(4): 353-368 (2013) - [c74]Jan Hartmann, Walter Stechele, Erik Maehle:
Self-adaptation for Mobile Robot Algorithms Using Organic Computing Principles. ARCS 2013: 232-243 - [c73]Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat:
A resource-aware nearest-neighbor search algorithm for k-dimensional trees. DASIP 2013: 80-87 - [c72]Florian Aschauer, Walter Stechele, Johannes Treis:
Dynamic Noise Estimation Approach for X-Ray Detectors on FPGAs. DSD 2013: 193-200 - [c71]Florian Aschauer, Walter Stechele, Johannes Treis:
FPGA Based Real-Time Data Processing DAQ System for the Mercury Imaging X-Ray Spectrometer. DSD 2013: 535-542 - [c70]Gregor Walla, Zaur Molotnikov, Hans-Ulrich Michel, Walter Stechele, Andreas Barthels, Andreas Herkersdorf:
A Design Space Exploration Framework For Automotive Embedded Systems And Their Power Management. ECMS 2013: 228-234 - [c69]Michael Feilen, Andreas Iliopoulos, Michael Vonbun, Walter Stechele:
Weighted partitioning of sequential processing chains for dynamically reconfigurable FPGAS. FPL 2013: 1-8 - [c68]David May, Walter Stechele:
A resource-efficient probabilistic fault simulator. FPL 2013: 1-4 - [c67]Jan Hartmann, Walter Stechele, Erik Maehle:
Self-reconfigurable Control Architecture for Complex Robots. GI-Jahrestagung 2013: 2742-2748 - [c66]Andreas Herkersdorf, Johny Paul, Ravi Kumar Pujari, Walter Stechele, Stefan Wallentowitz, Thomas Wild, Aurang Zaib:
Potentials and Challenges for Multi-Core Processors in Robotic Applications. GI-Jahrestagung 2013: 2749-2764 - [c65]Lingkan Gong, Oliver Diessel, Johny Paul, Walter Stechele:
RTL Simulation of High Performance Dynamic Reconfiguration: A Video Processing Case Study. IPDPS Workshops 2013: 106-113 - [c64]Tamara Seybold, Christian Keimel, Marion Knopp, Walter Stechele:
Towards an Evaluation of Denoising Algorithms with Respect to Realistic Camera Noise. ISM 2013: 203-210 - [c63]Michael Vonbun, Stefan Wallentowitz, Michael Feilen, Walter Stechele, Andreas Herkersdorf:
Evaluation of hop count advantages of network-coded 2D-mesh NoCs. PATMOS 2013: 134-141 - 2012
- [c62]Dirk Koch, Jim Tørresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, Walter Stechele:
Partial Reconfiguration on FPGAs in Practice - Tools and Applications. ARCS Workshops 2012: 297-319 - [c61]Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Rüdiger Dillmann:
Invasive Computing for robotic vision. ASP-DAC 2012: 207-212 - [c60]Sebastian Drössler, Michael Eichhorn, S. Holzknecht, Bernd Müller-Rathgeber, Holm Rauchfuss, Michael Zwick, Erwin M. Biebl, Klaus Diepold, Jörg Eberspächer, Andreas Herkersdorf, Walter Stechele, Eckehard G. Steinbach, R. Freymann, Karl-Ernst Steinberg, Hans-Ulrich Michel:
A Real-Time Capable Virtualized Information and Communication Technology Infrastructure for Automotive Systems. Advances in Real-Time Systems 2012: 275-306 - [c59]Michael Feilen, Andreas Iliopoulos, Matthias Ihmig, Walter Stechele:
Partitioning and context switching for a reconfigurable FPGA-based DAB receiver. DASIP 2012: 1-8 - [c58]Lothar Stolz, Matthias Ihmig, Walter Stechele:
An evaluation on using GPU coprocessing for software radios on a low-cost platform. DASIP 2012: 1-8 - [c57]Abdelmajid Bouajila, Abdallah Lakhtel, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf:
A low-overhead monitoring ring interconnect for MPSoC parameter optimization. DDECS 2012: 46-49 - [c56]Michael Feilen, Matthias Ihmig, Christian Schwarzbauer, Walter Stechele:
Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources. FPL 2012: 75-82 - [c55]David May, Walter Stechele:
An FPGA-based probability-aware fault simulator. ICSAMOS 2012: 302-309 - 2011
- [j4]Seunghan Han, Walter Stechele:
Default Reasoning for Forensic Visual Surveillance based on Subjective Logic and Its Comparison with L-Fuzzy Set Based Approaches. Int. J. Multim. Data Eng. Manag. 2(1): 38-86 (2011) - [c54]Walter Stechele, Jan Hartmann, Erik Maehle:
An approach to self-learning multicore reconfiguration management applied on Robotic Vision. DASIP 2011: 217-222 - [c53]Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf:
An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. DDECS 2011: 225-230 - [c52]Seunghan Han, Andreas Hutter, Walter Stechele:
A reasoning approach to enable abductive semantic explanation upon collected observations for forensic visual surveillance. ICME 2011: 1-7 - [c51]Juan Gómez-Luna, Holger Endt, Walter Stechele, José María González-Linares, José Ignacio Benavides, Nicolás Guil:
Egomotion compensation and moving objects detection algorithm on GPU. PARCO 2011: 183-190 - [c50]Holger Endt, Lothar Stolz, Martin Wechs, Walter Stechele:
A Model-Based Software Generation Approach Qualified for Heterogeneous GPGPU-Enabled Platforms. PARCO 2011: 217-223 - [p3]Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Andreas Herkersdorf:
Autonomic System on Chip Platform. Organic Computing 2011: 413-425 - [p2]Johannes Zeppenfeld, Abdelmajid Bouajila, Walter Stechele, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Andreas Herkersdorf:
Applying ASoC to Multi-core Applications for Workload Management. Organic Computing 2011: 461-472 - 2010
- [c49]Christopher Claus, Rehan Ahmed, Florian Altenried, Walter Stechele:
Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems. ARC 2010: 55-67 - [c48]Seunghan Han, Bonjung Koo, Andreas Hutter, Vinay D. Shet, Walter Stechele:
Subjective Logic Based Hybrid Approach to Conditional Evidence Fusion for Forensic Visual Surveillance. AVSS 2010: 337-344 - [c47]Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich:
A rapid prototyping system for error-resilient multi-processor systems-on-chip. DATE 2010: 375-380 - [c46]Robert Hartl, Andreas J. Rohatschek, Walter Stechele, Andreas Herkersdorf:
Architectural Vulnerability Factor Estimation with Backwards Analysis. DSD 2010: 605-612 - [c45]Johannes Zeppenfeld, Abdelmajid Bouajila, Andreas Herkersdorf, Walter Stechele:
Towards Scalability and Reliability of Autonomic Systems on Chip. ISORC Workshops 2010: 73-80 - [c44]Seunghan Han, Bonjung Koo, Walter Stechele:
Subjective Logic Based Approach to Modeling Default Reasoning for Visual Surveillance. ICSC 2010: 112-119 - [c43]Benjamin Kormann, Antje Neve, Gudrun Klinker, Walter Stechele:
Stereo Vision based Vehicle Detection. VISAPP (2) 2010: 431-438 - [c42]Seunghan Han, Bonjung Koo, Andreas Hutter, Walter Stechele:
Forensic reasoning upon pre-obtained surveillance metadata using uncertain spatio-temporal rules and subjective logic. WIAMIS 2010: 1-4 - [p1]Christopher Claus, Walter Stechele:
AutoVision - Reconfigurable Hardware Acceleration for Video-Based Driver Assistance. Dynamically Reconfigurable Systems 2010: 375-394 - [i3]Walter Stechele, Christopher Claus, Andreas Laika:
Lessons Learned from last 4 Years of Reconfigurable Computing. Dynamically Reconfigurable Architectures 2010
2000 – 2009
- 2009
- [j3]Paul Zuber, Othman Bahlous, Thomas Ilnseher, Michael Ritter, Walter Stechele:
Wire Topology Optimization for Low Power CMOS. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 1-11 (2009) - [c41]Christopher Claus, Robert Huitl, Joachim Rausch, Walter Stechele:
Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation. FPL 2009: 138-145 - [c40]Andreas Laika, Adrian Taruttis, Walter Stechele:
Segmentation Through Edge-linking - Segmentation for Video-based Driver Assistance Systems. IMAGAPP 2009: 43-49 - [c39]Seunghan Han, Andreas Hutter, Walter Stechele:
Toward contextual forensic retrieval for visual surveillance: Challenges and an architectural approach. WIAMIS 2009: 201-204 - 2008
- [c38]Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele:
Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. ARC 2008: 148-158 - [c37]Nicolas Alt, Christopher Claus, Walter Stechele:
Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments. DATE 2008: 176-181 - [c36]Jürgen Becker, Michael Hübner, Robert Esser, Andreas Herkersdorf, Walter Stechele, Vera Lauer:
Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. DATE 2008 - [c35]Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker:
Fine grain reconfigurable architectures. FPL 2008: 348 - [c34]Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker:
A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. FPL 2008: 535-538 - [c33]Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich:
A comparison of embedded reconfigurable video-processing architectures. FPL 2008: 587-590 - [c32]Andreas Herkersdorf, Walter Stechele, Christian Müller-Schloer, Hartmut Schmeck:
Workshop "Adaptive and Organic Systems". GI Jahrestagung (2) 2008: 731-732 - [c31]Johannes Zeppenfeld, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf:
Learning Classifier Tables for Autonomic Systems on Chip. GI Jahrestagung (2) 2008: 771-778 - [c30]Colin Estermann, Walter Stechele, Robert Kutka, Andreas Hutter:
Luminance Correction in Stereo Correspondence Based Structure from Motion. WIAMIS 2008: 179-182 - 2007
- [j2]Christopher Claus, Walter Stechele, Andreas Herkersdorf:
Autovision - A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance Systems (Autovision - Eine zur Laufzeit rekonfigurierbare MPSoC Architektur für zukünftige Fahrerassistenzsysteme). it Inf. Technol. 49(3): 181- (2007) - [c29]Christopher Claus, Johannes Zeppenfeld, Florian Helmut Müller, Walter Stechele:
Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system. DATE 2007: 498-503 - [c28]Christopher Claus, Florian Helmut Müller, Johannes Zeppenfeld, Walter Stechele:
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration. IPDPS 2007: 1-7 - [c27]Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele:
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. ISVLSI 2007: 41-46 - [c26]Andreas Laika, Walter Stechele:
A review of different object recognition methods for the application in driver assistance systems. WIAMIS 2007: 10 - [i2]Walter Stechele, L. Alvado Cárcel, Stephan Herrmann, J. Lidón Simón:
A Coprocessor for Accelerating Visual Information Processing. CoRR abs/0710.4823 (2007) - 2006
- [c25]Christopher Claus, Florian Helmut Müller, Walter Stechele:
Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro. ARCS Workshops 2006: 122-131 - [c24]Andreas Herkersdorf, Walter Stechele:
AutoVision: flexible processor architecture for video-assisted driving. DATE 2006: 556 - [c23]Miljan Vuletic, Paolo Ienne, Christopher Claus, Walter Stechele:
Multithreaded virtual-memory-enabled reconfigurable hardware accelerators. FPT 2006: 197-204 - [c22]Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf:
An Architecture for Runtime Evaluation of SoC Reliability. GI Jahrestagung (1) 2006: 177-184 - [c21]Abdelmajid Bouajila, Andreas Bernauer, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele:
Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs. BICC 2006: 107-113 - [c20]Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel:
Organic Computing at the System on Chip Level. VLSI-SoC 2006: 338-341 - [i1]Walter Stechele:
Dynamically Reconfigurable Systems-on-Chip. Dynamically Reconfigurable Architectures 2006 - 2005
- [c19]Gabriel Mihai Lipsa, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele:
Towards a Framework and a Design Methodology for Autonomous SoC. ARCS Workshops 2005: 101-108 - [c18]Walter Stechele, L. Alvado Cárcel, Stephan Herrmann, J. Lidón Simón:
A Coprocessor for Accelerating Visual Information Processing. DATE 2005: 26-31 - [c17]Paul Zuber, Armin Windschiegl, Raúl Medina Beltrán de Otálora, Walter Stechele, Andreas Herkersdorf:
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization. DATE 2005: 986-987 - [c16]Paul Zuber, Florian Helmut Müller, Walter Stechele:
Optimization Potential of CMOS Power by Wire Spacing. GI Jahrestagung (1) 2005: 344-348 - [c15]Gabriel Mihai Lipsa, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele:
Towards a Framework and a Design Methodology for Autonomic SoC. ICAC 2005: 391-392 - [c14]Paul Zuber, Peter Gritzmann, Michael Ritter, Walter Stechele:
The Optimal Wire Order for Low Power CMOS. PATMOS 2005: 674-683 - 2004
- [c13]Walter Stechele, Stephan Herrmann, Andreas Herkersdorf:
Towards a Dynamically Reconfigurable System-on-Chip Platform for Video Signal Processing. ARCS Workshops 2004: 225-234 - 2003
- [c12]Walter Stechele:
Performance Optimization of Color Segmentation Algorithms. SIP 2003: 292-297 - 2002
- [c11]Ulrich Niedermeier, Jörg Heuer, Andreas Hutter, Walter Stechele:
MPEG-7 Binary Format for XML Dat. DCC 2002: 467 - [c10]Torsten Mahnke, Walter Stechele, Martin Embacher, Wolfgang Hoeld:
Impact of technology evolution on dual supply voltage scaling and gate resizing in power-driven logic synthesis. ICECS 2002: 697-700 - [c9]Torsten Mahnke, Sebastian Panenka, Martin Embacher, Walter Stechele, Wolfgang Hoeld:
Efficiency of dual supply voltage logic synthesis for low power in consideration of varying delay constraint strictness. ICECS 2002: 701-704 - [c8]Michael Eiermann, Walter Stechele:
Efficient power modeling techniques for combinational and sequential RTL macroblocks. ICECS 2002: 705-708 - [c7]Armin Windschiegl, Torsten Mahnke, Michael Eiermann, Walter Stechele, Paul Zuber:
A wire load model considering metal layer properties. ICECS 2002: 765-768 - [c6]Ulrich Niedermeier, Jörg Heuer, Andreas Hutter, Walter Stechele, André Kaup:
An MPEG-7 tool for compression and streaming of XML data. ICME (1) 2002: 521-524 - [c5]Michael Eiermann, Walter Stechele:
Novel modeling techniques for RTL power estimation. ISLPED 2002: 323-328 - [c4]Armin Windschiegl, Paul Zuber, Walter Stechele:
Exploiting Metal Layer Characteristics for Low-Power Routing. PATMOS 2002: 55-64 - [c3]Torsten Mahnke, Walter Stechele, Wolfgang Hoeld:
Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment. PATMOS 2002: 146-155 - 2000
- [c2]Andreas Hutter, Georg Giebel, Walter Stechele:
A coprocessor architecture implementing the MPEG-4 visual core profile for mobile multimedia applications. ISCAS 2000: 176-179
1990 – 1999
- 1999
- [j1]Stephan Herrmann, Hubert Mooshofer, Harald Dietrich, Walter Stechele:
A video segmentation algorithm for hierarchical object representations and its implementation. IEEE Trans. Circuits Syst. Video Technol. 9(8): 1204-1215 (1999) - 1997
- [c1]Peter M. Kuhn, Andreas Weisgerber, Robert Poppenwimmer, Walter Stechele:
A flexible VLSI architecture for variable block size segment matching with luminance correction. ASAP 1997: 479-488
Coauthor Index
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