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ORCID33rd Asian Test Symposium 2024: Ahmedabad, India
- 33rd IEEE Asian Test Symposium, ATS 2024, Ahmedabad, India, December 17-20, 2024. IEEE 2024, ISBN 979-8-3315-2916-1
- Kamilia Tahraoui, T. Vayssade, François Lefèvre, Laurent Latorre, Florence Azaïs:
Low-cost generation of RF test stimuli from baseband digital signals. 1-6 - Shubham Shrivastava, Sainath Kartik Yeshagol, Harry Linzer:
Methods and Apparatus to Support Multiple Synchronous Clocks with a Single Clock Mesh. 1-4 - Raghavendra Kumar Sakali, Noor Mahammad Sk:
Preferential Fault-Tolerant based TF32 Floating Point Adder for Mission Critical Systems. 1-5 - Sriram Ranga, Rui Mao, Debjyoti Bhattacharjee, Erik Cambria, Anupam Chattopadhyay:
RTL Agent: An Agent-Based Approach for Functionally Correct HDL Generation via LLMs. 1-6 - Jugal Gandhi
, Diksha Shekhawat, M. Santosh, Jaya Dofe, Jai Gopal Pandey:
Large Language Model Driven Logic Locking: A Generative Approach to Secure IC Design. 1-4 - Sujeet Maurya, Gedupudi Bharghav Ram:
Optimizing LBIST Run Time for a Safety Critical SoC: A Practical Approach. 1-5 - Giuseppe Esposito, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
Evaluating Different Fault Injection Abstractions on the Assessment of DNN SW Hardening Strategies. 1-6 - Jayesh Popat, Ramesh Devani, Jay Gohil:
Improving At-Speed Test Coverage without compromising Test Time and reducing Test Cost in multi-partition SCAN Design. 1-5 - Mostafa Hosseini, Ali Azarpeyvand, Tara Ghasempouri:
PATROL: An Evolutionary APproach to Automatic Test Pattern Generation for Hardware TROjan Detection Leveraging PSO-GA Hybrid Techniques. 1-6 - Anirban Paul, Jimit Gadhia, Aashish Agrawal, Anuj Srivastava, Sandip Paul, Ashutosh Mishra, Ashok Kumar, Sanjeev Mehta, Ashish Mishra:
Automated System for Testing and Result Analysis for Payload Controller. 1-6 - Devendra Mishra, Rikteem Bhowmick, Rama Theja, Kapil Jaiswal, Devesh Kumar, Nilesh Pandey, Aishik Acharya, Bappaditya Sankhari, Sachin Barthwal:
Experimental Realization of Quantum Memory and EPS-QKD. 1-6 - Jamuna S, Madhura R, Kishore Kumar K, Murali S. Bharadwaja:
Design and Simulation of Fault Detection Technique for NAND Based Memory Array. 1-4 - Bhargab B. Bhattacharya, Debesh K. Das, Subhajit Chatterjee, Hafizur Rahaman:
Fault Testing in AI-Accelerators: A Review. 1-6 - Fatemeh Shirinzadeh, Kamalika Datta, Saeideh Shirinzadeh, Abhoy Kole, Rolf Drechsler:
Towards Formal Verification for MAC-based In-Memory Computing. 1-6 - Pervez Garg, Piyushkumar M. Chaniyara:
Power Aware test methodology for Test Power hungry complex SoCs. 1-4 - Mohamed Yaqub A, Sudikshan S, Navin Balaji E, Adarsh A, M. Gayathri, Amlan Chakrabarti:
Quantum Key Distribution-Based Framework for Securing Encrypted Communications in Address Resolution Protocol Packet Capture. 1-6 - Jay K. Gohil, Ramesh B. Devani, Jayesh Popat:
A Novel Differential 12T SRAM Bit-cell Structure with Improved SNM in 16nm FinFET Technology. 1-7 - Rijoy Mukherjee, Sneha Swaroopa, Rajat Subhra Chakraborty:
Security Vulnerabilities in AI Hardware: Threats and Countermeasures. 1-6 - Vaibhav Mishra, Bharath Nandakumar, Sameer Chillarige:
High performance advanced fault model diagnosis. 1-7 - Niranjana J. Ithal, Natarajan Adharsh, Anurup P, K. Sudeendra Kumar:
A Complete Security Protocol To Safeguard IJTAG Architecture. 1-6 - Samira Nazari, Mahdi Taheri, Ali Azarpeyvand, Mohsen Afsharchi, Tara Ghasempouri, Christian Herglotz, Masoud Daneshtalab, Maksim Jenihhin:
FORTUNE: A Negative Memory Overhead Hardware-Agnostic Fault TOleRance TechniqUe in DNNs. 1-6 - Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, F. Lalchhandama, Kamalika Datta, Rolf Drechsler, Indranil Sengupta:
Improving Self-Fault-Tolerance Capability of Memristor Crossbar Using a Weight-Sharing Approach. 1-6 - Sutirtha Bhattacharyya, Sutharshanan B. G, Chandan Karfa:
LLM vs HLS for RTL Code Generation: Friend or Foe? 1-6 - Hanxu Feng, Yuanhang Bu, Jing Zhou, Shuo Wang, Zhuoli Wang, Lei Chen:
Post-silicon Trace Signal Selection Using Genetic Algorithm. 1-4 - Habibur Rahaman, Atri Chatterjee, Swarup Bhunia:
SAMURAI: A Framework for Safeguarding Against Malicious Usage and Resilience of AI. 1-6 - Navajit Singh Baban, Mohammed Abdelhameed, Mahmoud Elbeh, Khalil Ramadi, Yong-Ak Song, Sukanta Bhattacharjee, Ramesh Karri, Krishnendu Chakrabarty:
Carbon Quantum Dot Fluorescent Stickers for Biochip Authentication. 1-6 - Nishan Xie, Hongping Ren, Rui Li, Qian Dong, Lingzhong Meng:
A Formal Approach and Testing Process for Failure Modes in Intelligent Algorithms. 1-6 - Zhenghao Li, Yang Zhang, Xing Hu, Jialong Song, Shaoqing Li, Bin Liang:
SFCM-HT: Hardware Trojan Detection Based on Sequence Features with a Combination Model. 1-6 - R. Madhura, Peram Varshitha, S. Nikitha, Niveditha K. M., Mayuri Bhat K.:
RTL design of 16-bit RISC Processor Using Vedic Mathematics. 1-4 - Vasavi Ghanta, Vinodh J. Rakesh:
A Novel Multi-Scope Characterization Method for Automotive LPDDR4 Controller. 1-7 - Sudipta Paria, Pravin Gaikwad, Aritra Dasgupta, Swarup Bhunia:
LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection. 1-6 - Habibur Rahaman, Atri Chatterjee, Swarup Bhunia:
Secure AI Systems: Emerging Threats and Defense Mechanisms. 1-6 - Jithesh Pothandy Karayi, Vinodh J. Rakesh, Prince V. Thachil, Timmy Eapen Peter, Vasavi Ghanta:
Automotive Microcontroller Characterization Hardware - Challenges and Solutions. 1-6 - Jiaqi Guo, Wei Xiong, Jian Wang, Jinmei Lai:
Testing Method for Embedded UltraRAM in Field Programmable Gate Arrays. 1-6 - Jiaping Tang, Zizhen Liu, Jianan Mu, Feng Gu, Mingjun Wang, Wenxing Li, Jing Ye, Xiaowei Li, Huawei Li:
Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction. 1-6 - Vyom Kumar Gupta, Abhishek Yadav, Masahiro Fujita, Binod Kumar:
LLM-aided Front-End Design Framework For Early Development of Verified RTLs. 1-6 - Wei-Kai Liu, Jonti Talukdar, Benjamin Tan, Krishnendu Chakrabarty:
Effective Runtime Fault Detection for DNN Accelerators. 1-6 - Venkata Sreekanth Balijabudda, Indrajit Chakrabarti, Rajat Subhra Chakraborty:
Design, Implementation and Characterization of a Novel Robust-by-Construction Arbiter PUF Circuit on Xilinx FPGAs. 1-6 - Tanusree Kaibartta, Rajiv Murmu, Debesh Kumar Das:
A Novel TSV Repair Framework for 3-D Stacked ICs. 1-6 - Nilotpola Sarma, E. Bhawani Eswar Reddy, Chandan Karfa:
Security Concerns of Machine Learning Hardware. 1-6 - Yingchun Lu, Enpu Xu, Huaguo Liang, Cuiyun Jiang, Lixiang Ma, Liang Yao:
MTCX: Ultra-high Throughput TRNG Based on Mesh topology of Coupled-XOR. 1-4 - Zhaoming Jin, Zhixin Shi:
Boosting self-repair workflow with brainstorming for code generation. 1-6 - Wei-Po Huang, Shi-Yu Huang, Chi-Kang Chen, Siang-Cheng Huang:
Trojan Horse Detection for RISC-V Cores Using Cross-Auditing. 1-6 - Saman Aijaz Siddiqui, Uzair Ruhulamin Patel, Utsav Jana, Binod Kumar:
MEMFD: A Multi-EDT Multi-Fault Scan Chain Diagnosis Methodology with Deep Learning. 1-6 - Jayeeta Chaudhuri, Hassan Nassar, Dennis R. E. Gnad, Jörg Henkel, Mehdi B. Tahoori, Krishnendu Chakrabarty:
Hacking the Fabric: Targeting Partial Reconfiguration for Fault Injection in FPGA Fabrics. 1-6 - Bhavin Bhavani, Anupam Mathur, Sreeja Rajendran, Vinay Palaparthy, Yash Agrawal:
Enhancing SRAM Array Security Through Transmission Gate-Based Logic Obfuscation. 1-4 - Rolf Drechsler, Christina Plump, Martha Schnieber:
The Future is Hybrid: Next Generation Data Structures for Formal Verification. 1-6 - Yutao Sun, Zhijun Wang, Zean Huang, Liping Liang:
An FPGA-Based Emulation Platform for Functional Safety Verification in Automotive SoC Systems. 1-6 - Yang Zeng, Xiaole Cui:
A Testability Improvement Method of Combinational Circuits Based on the SDC Conditions. 1-6 - Roshwin Sengupta, Ilia Polian, John P. Hayes:
Fault Tolerance in Stochastic Circuits for Recurrent Sequential Neural Networks. 1-6 - Md. Sihabul Islam, Ryota Eguchi, Michiko Inoue:
Reliability Enhancement of Memristor-Based Neural Networks with Fault-Injected Training. 1-6 - Khushboo Qayyum, Sallar Ahmadi-Pour, Chandan Kumar Jha, Muhammad Hassan, Rolf Drechsler:
LLMs for Hardware Verification: Frameworks, Techniques, and Future Directions. 1-6 - Himanshu Miriyala, Rishabh Pal, Arijit Sharma:
Finite element analysis (FEA) based design optimization of ultrastable, high finesse optical cavities for portable optical atomic clock applications. 1-6 - Karthik Pandaram, Hussam Amrouch, Ilia Polian:
Optimized Detection of Marginal Defects in Standard Cells Using Unsupervised Learning. 1-6 - Diptanshu Bagchi, Habibur Rahaman, Sudip Ghosh, Subhajit Chatterjee:
ML Based Diagnosis for Fault Location in Digital Circuits. 1-6
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