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ORCIDJinmei Lai 0001
Person information
- affiliation: Fudan University, School of Microelectronics, State Key Laboratory of ASIC and System, Shanghai, China
Other persons with the same name
- Jin-Mei Lai (aka: Jinmei Lai) — disambiguation page
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2020 – today
- 2025
[j19]Yanze Li, Jian Wang, Jinmei Lai:
Shrink eFPGA tile area by using custom cells and optimizing routing congestion. Microelectron. J. 156: 106544 (2025)- [c56]Wenwei Chen
, Lin Ye, XiaoTong Zhao, Tongshu Ding, Jian Wang, Jinmei Lai:
An Efficient Traversal Method for FPGA Interconnect Testing Based on Regular Routing. FPGA 2025: 67-77 - 2024
- [j18]Jiacheng Cao, Wei Xiong, Jie Lu, Peilin Chen, Jian Wang, Jinmei Lai, Miaoqing Huang:
An optimized EEGNet processor for low-power and real-time EEG classification in wearable brain-computer interfaces. Microelectron. J. 145: 106134 (2024) - [j17]Wei Xiong, Jiacheng Cao, Yaozhang Liu, Jian Wang, Jinmei Lai, Miaoqing Huang:
A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1058-1071 (2024) - [c55]Jiaqi Guo, Wei Xiong, Jian Wang, Jinmei Lai:
Testing Method for Embedded UltraRAM in Field Programmable Gate Arrays. ATS 2024: 1-6 - 2023
- [j16]Qingliang Liu, Shuai Zhou, Jinmei Lai:
EdgeMedNet: Lightweight and Accurate U-Net for Implementing Efficient Medical Image Segmentation on Edge Devices. IEEE Trans. Circuits Syst. II Express Briefs 70(12): 4329-4333 (2023) - [c54]Jiacheng Cao, Ziyi Yang, Jie Lu, Jinmei Lai:
A High-Performance YOLOV5 Accelerator for Object Detection with Near Sensor Intelligence. ASICON 2023: 1-4 - [c53]Yanze Li, Zeyu Sun, Jianfan Zhang, Zhichao Wei, Jian Wang, Jinmei Lai:
An Accurate Area Model for FPGA Circuits at Advanced Technologies. ASICON 2023: 1-4 - [c52]Honghong Long, Yu Bai, Yanze Li, Jian Wang, Jinmei Lai:
Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm. ASICON 2023: 1-4 - 2022
- [j15]Yanze Li, Yufan Zhang, Jiafeng Liu, Jun Gong, Jian Wang, Jinmei Lai, Xinxuan Tao, Gang Qu:
AutoTEA: An Automated Transistor-level Efficient and Accurate design tool for FPGA design. Integr. 87: 231-240 (2022) - [j14]Huanlin Luo, Haowen Zhu, Shengyang Liu, Yichuan Liu, Xinzhong Zhu, Jinmei Lai:
3-D Auxiliary Classifier GAN for Hyperspectral Anomaly Detection via Weakly Supervised Learning. IEEE Geosci. Remote. Sens. Lett. 19: 1-5 (2022) - [j13]Qingliang Liu, Jinmei Lai, Jiabao Gao:
An Efficient Channel-Aware Sparse Binarized Neural Networks Inference Accelerator. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1637-1641 (2022) - [c51]Wei Xiong, Yanze Li, Changpeng Sun, Huanlin Luo, Jiafeng Liu, Jian Wang, Jinmei Lai, Gang Qu:
An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique. ACM Great Lakes Symposium on VLSI 2022: 275-280 - 2021
- [j12]Jiabao Gao, Yuchen Yao, Zhengjie Li, Jinmei Lai:
FCA-BNN: Flexible and Configurable Accelerator for Binarized Neural Networks on FPGA. IEICE Trans. Inf. Syst. 104-D(8): 1367-1377 (2021) - [j11]Zhengjie Li, Jiabao Gao, Jinmei Lai:
HBDCA: A Toolchain for High-Accuracy BRAM-Defined CNN Accelerator on FPGA with Flexible Structure. IEICE Trans. Inf. Syst. 104-D(10): 1724-1733 (2021) - [c50]Yanze Li, Yufan Zhang, Jiafeng Liu, Jian Wang, Jinmei Lai, Gang Qu:
AutoTEA: Automated Transistor-level Efficient and Accurate Optimization for GRM FPGA Design. FCCM 2021: 256 - [c49]Qingliang Liu, Jiabao Gao, Jinmei Lai:
TCP-Net: Minimizing Operation Counts of Binarized Neural Network Inference. ISCAS 2021: 1-5 - 2020
- [c48]Jiliang Zhang, Shuang Peng, Yupeng Hu, Fei Peng, Wei Hu, Jinmei Lai, Jing Ye, Xiangqi Wang:
HRAE: Hardware-assisted Randomization against Adversarial Example Attacks. ATS 2020: 1-6 - [c47]Chengyu Hu, Qinghua Duan, Peng Lu, Wei Liu, Jian Wang, Jinmei Lai:
INTB: A New FPGA Interconnect Model for Architecture Exploration. FPGA 2020: 325 - [c46]Yufan Zhang, Zhengjie Li, Jian Wang, Jinmei Lai:
FPTLOPT: An Automatic Transistor-Level Optimization Tool for GRM FPGA. FPGA 2020: 325 - [c45]Chengyu Hu, Qinghua Duan, Peng Lu, Wei Liu, Jian Wang, Jinmei Lai:
A Tile-based Interconnect Model for FPGA Architecture Exploration. ACM Great Lakes Symposium on VLSI 2020: 113-118 - [c44]Jia-Bao Gao, Jian Wang, Md Tanvir Arafin, Jin-Mei Lai:
FABLE-DTS: Hardware-Software Co-Design of a Fast and Stable Data Transmission System for FPGAs. SoCC 2020: 207-212
2010 – 2019
- 2019
- [c43]Timothy Dunlap, Gang Qu, Jinmei Lai:
A Polymorphic Circuit Interoperability Framework. ASICON 2019: 1-4 - [c42]Xinyu He, Xie Xie, Jinmei Lai, Jian Wang:
A Web-based Waveform Viewer for BR0101 Chip Testing Platform. ASICON 2019: 1-4 - [c41]Wei Liu, Weilin Cong, Chengyu Hu, Peng Lu, Jinmei Lai:
Balance of memory footprint and runtime for high-density routing in large-scale FPGAs. ASICON 2019: 1-4 - [c40]Jiafeng Liu, Zhiyin Lu, Xie Xie, Jian Wang, Jinmei Lai:
An Exponential Dynamic Weighted Fair Queuing Algorithm for Task Scheduling in Chip Verification Platform. ASICON 2019: 1-4 - [c39]Zhi-Yin Lu, Jia-Feng Liu, Yunbing Pang, Zhengjie Li, Yufan Zhang, Jin-Mei Lai, Jian Wang:
A Low-delay Configurable Register for FPGA. ASICON 2019: 1-4 - [c38]Huanlin Luo, Yunbo Liu, Hai Ren, Tiantian Zhang, Jian Wang, Jinmei Lai:
An FPGA-based log-structure Flash memory system for space exploration. ASICON 2019: 1-4 - [c37]Yunbing Pang, Jiqing Xu, Zhiyin Lu, Zhengjie Li, Yufan Zhang, Jinmei Lai:
Research on Area Modeling Methodology for FPGA Interconnect Circuits. ASICON 2019: 1-4 - [c36]Xie Xie, Qinghua Duan, Jiafeng Liu, Jian Wang, Jinmei Lai:
Design and implementation of Serial ATA pbysical layer on FPGA. ASICON 2019: 1-4 - [c35]Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Jian Wang, Jinmei Lai:
Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits. FPGA 2019: 121 - [c34]Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Chengyu Hu, Jian Wang, Jinmei Lai:
An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization. ACM Great Lakes Symposium on VLSI 2019: 93-98 - [c33]Chengyu Hu, Qinghua Duan, Liran Hu, Peng Lu, Zhengjie Li, Meng Yang, Jian Wang, Jinmei Lai:
An Analytical-based Hybrid Algorithm for FPGA Placement. ACM Great Lakes Symposium on VLSI 2019: 351-354 - 2018
- [j10]Hanyang Xu, Jian Wang, Jinmei Lai:
Design of a power efficient self-adaptive LVDS driver. IEICE Electron. Express 15(5): 20171276 (2018) - [j9]Chengyu Hu, Peng Lu, Meng Yang, Jian Wang, Jinmei Lai:
A SA-based parallel method for FPGA placement. IEICE Electron. Express 15(24): 20180943 (2018) - 2017
- [c32]Chuanliang Kang, Pei Yang, Jian Wang, Jinmei Lai:
A deep research on the chip verification platform based on network. ASICON 2017: 323-326 - [c31]Jiaqi Gu, Ruoyao Wang, Jian Wang, Jinmei Lai, Qinghua Duan:
Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration. ASICON 2017: 402-405 - [c30]Yuchen Yao, Zhiqian Zhang, Zhen Yang, Jian Wang, Jinmei Lai:
FPGA-based convolution neural network for traffic sign recognition. ASICON 2017: 891-894 - 2016
- [j8]Hanyang Xu, Jian Wang, Jinmei Lai:
Prototyping design of a flexible DSP block with pipeline structure for FPGA. IEICE Electron. Express 13(17): 20160676 (2016) - [j7]Yuanlong Xiao, Jian Wang, Jinmei Lai:
A universal automatic on-chip measurement of FPGA's internal setup and hold times. IEICE Electron. Express 13(23): 20160810 (2016) - [c29]Zhen Yang, Jian Wang, Meng Yang, Jinmei Lai:
Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only). FPGA 2016: 280 - 2015
- [j6]Zhen Yang, Chuanzeng Liang, Jian Wang, Jinmei Lai:
A new automatic method for testing interconnect resources in FPGAs based on general routing matrix. IEICE Electron. Express 12(20): 20150747 (2015) - [c28]Yuanpei Gao, Haijiang Ye, Jian Wang, Jinmei Lai:
FPGA bitstream compression and decompression based on LZ77 algorithm and BMC technique. ASICON 2015: 1-4 - [c27]Fang Sun, Jin-Mei Lai:
Iterative optimization algorithm for sound localization. ASICON 2015: 1-4 - [c26]Yuanlong Xiao, Jian Wang, Jinmei Lai:
A power efficient current-mode differential driver for FPGAs. ASICON 2015: 1-4 - 2014
- [j5]Meng Yang, Jinmei Lai, A. E. A. Almaini:
An Architecture Independent Packing Method for LUT-based Commercial FPGA. J. Comput. 9(5): 1131-1137 (2014) - [c25]Lei Li, Jian Wang, Jinmei Lai:
Novel FPGA clock network with low latency and skew (abstract only). FPGA 2014: 252 - 2013
- [j4]Meng Yang, Jiarong Tong, Jinmei Lai:
Optimisation of Fixed Polarity Canonical Or-Coincidence Expansions. J. Comput. 8(10): 2520-2526 (2013) - [j3]Meng Yang, Jinmei Lai:
Optimisation of Mixed Polarity Reed-Muller Functions. J. Softw. 8(11): 2770-2774 (2013) - [c24]Jinmei Lai, Yanquan Luo, Qi Shao, Lichun Bao, Xueling Liu:
A high-resolution TDC implemented in a 90nm process FPGA. ASICON 2013: 1-3 - [c23]Huagang Li, Jian Wang, Jinmei Lai:
Weight-based FPGA placement algorithm with wire effect considered. ASICON 2013: 1-4 - [c22]Lei Li, Jian Wang, Jinmei Lai:
Improved unified interconnect unit for high speed and scalable FPGA. ASICON 2013: 1-4 - [c21]Xinrui Zhang, Jian Wang, Dan Chen, Jinmei Lai, Lichun Bao, Xueling Liu:
The timing control design of 65nm block RAM in FPGA. ASICON 2013: 1-4 - [c20]Jinsong Mao, Hao Zhou, Haijiang Ye, Jinmei Lai:
FPGA bitstream compression and decompression using LZ and golomb coding (abstract only). FPGA 2013: 265 - [c19]Chun Zhu, Qiuli Li, Jian Wang, Jinmei Lai:
A novel multithread routing method for FPGAs (abstract only). FPGA 2013: 269 - [c18]Meng Yang, Jinmei Lai, Jiarong Tong:
Yet Another Many-Objective Clustering (YAMO-Pack) for FPGA CAD. FPL 2013: 1-4 - [c17]Chun Zhu, Jian Wang, Jinmei Lai:
A novel net-partition-based multithread FPGA routing method. FPL 2013: 1-4 - [c16]Jun Rong Wang, Dan Wang, Jin-Mei Lai:
A hierarchical parallel evolvable hardware based on network on chip. ReConFig 2013: 1-6 - 2012
- [j2]Liyun Wang, Chun Zhang, Liguang Chen, Jinmei Lai, Jiarong Tong:
A novel memristor-based rSRAM structure for multiple-bit upsets immunity. IEICE Electron. Express 9(9): 861-867 (2012) - [c15]Yong Fu, Chi Wang, Liguang Chen, Jinmei Lai:
A novel full coverage test method for CLBs in FPGA (abstract only). FPGA 2012: 267 - 2011
- [c14]Lei Li, Jian Wang, Yuan Wang, Jinmei Lai:
Research on design method of scalable Configurable IP Core. AHS 2011: 50-57 - [c13]Zhidong Mao, Liguang Chen, Yuan Wang, Jinmei Lai:
A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain. ASICON 2011: 67-70 - [c12]Xiangzhi Meng, Liguang Chen, Hao Zhou, Jian Wang, Meng Yang, Jinmei Lai:
FPGA interconnect timing library based on the statistical method. ASICON 2011: 393-396 - [c11]Xinrui Zhang, Liguang Chen, Liyun Wang, Jian Wang, Jinmei Lai:
The design and verification of SEU-hardened configurable DFF. ASICON 2011: 937-940
2000 – 2009
- 2009
- [c10]HuaQiu Yang, Liguang Chen, ShaoTeng Liu, HaiXiang Bu, Yuan Wang, Jinmei Lai:
A Flexible Bit-Stream Level Evolvable Hardware Platform Based on FPGA. AHS 2009: 51-56 - [c9]Fang Wu, Huowen Zhang, Lei Duan, Jinmei Lai, Yuan Wang, Jiarong Tong:
A delay-optimized universal FPGA routing architecture. ASP-DAC 2009: 135-136 - [c8]JIanDe Yu, Jinmei Lai:
A novel minloop SB design to improve FPGA routability. FPGA 2009: 286 - 2008
- [j1]Wei Cao, Hui Hou, Jiarong Tong, Jinmei Lai, Hao Min:
A high-performance reconfigurable VLSI architecture for vbsme in H.264. IEEE Trans. Consumer Electron. 54(3): 1338-1345 (2008) - [c7]Yabin Wang, Jing Xie, Jinmei Lai, Jiarong Tong:
Design and implementation of the configuration circuit for FDP FPGA. APCCAS 2008: 696-700 - [c6]Wei Cao, Hui Hou, Jinmei Lai, Jiarong Tong, Hao Min:
A novel dynamic reconfigurable VLSI architecture for H.264 transforms. APCCAS 2008: 1810-1813 - [c5]Hui Hou, Wei Cao, Fan-jiong Zhang, Jinmei Lai, Jiarong Tong:
High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform. ICECS 2008: 486-489 - [c4]Wei Cao, Hui Hou, Jinmei Lai, Jiarong Tong, Hao Min:
A high-performance reconfigurable 2-D transform architecture for H.264. ICECS 2008: 606-609 - 2005
- [c3]Chi Huang, Xinyu Wu, Jinmei Lai, Chengshou Sun, Gang Li:
A design of high speed double precision floating point adder using macro modules. ASP-DAC 2005: 11-12 - [c2]Fei Wang, Jianyu Zhang, Xuan Wang, Jinmei Lai, Chengshou Sun:
Design of A 2.4-GHz integrated frequency synthesizer. ASP-DAC 2005: 21-22 - 2003
- [c1]Xinyu Wu, Zaiman Chen, Jinmei Lai, Qianling Zhang, Omar Wing, Junyan Ren:
Periodic steady-state analysis of coupled ODE-AE-CGE systems for MOS RF autonomous circuit simulation. ASP-DAC 2003: 885-890
Coauthor Index
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