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ORCIDCASES 2000: San Jose, California, USA
- Proceedings of the 2000 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2000, San Jose, California, USA, November 7-18, 2000. ACM 2000, ISBN 1-58113-338-3
- Amir Pnueli:
Rigorous development of embedded systems. 1 - Daniel Weil, Valérie Bertin, Etienne Closse, Michel Poize, Patrick Venier, Jacques Pulou:
Efficient compilation of ESTEREL for real-time embedded systems. 2-8 - Fridtjof Siebert:
Eliminating external fragmentation in a non-moving garbage collector for Java. 9-17 - Jeff Tsay, Christopher Hylands, Edward A. Lee:
A code generation framework for Java component-based designs. 18-25 - Jürgen Teich, Ralph Weper, Dirk Fischer, Stefan Trinkert:
A joined architecture/compiler design environment for ASIPs. 26-33 - Koen Danckaert, Francky Catthoor, Hugo De Man:
A preprocessing step for global loop transformations for data transfer optimization. 34-40 - Michel Barreteau, Juliette Mattioli, Thierry Grandpierre, Christophe Lavarenne, Yves Sorel, Philippe Bonnot, Philippe Kajfasz:
PROMPT: a mapping environment for telecom applications on "system-on-a-chip". 41-47 - Antti Takko, Marko Hännikäinen, Jarno Knuutila, Timo Hämäläinen, Jukka Saarinen:
Embedding SDL implemented protocols into DSP. 48-56 - Timothy J. Callahan, John Wawrzynek:
Adapting software pipelining for reconfigurable computing. 57-64 - Randall S. Janka, Linda M. Wills:
Specification and synthesis of real-time embedded distributed and parallel multiprocessor-based signal processing systems. 65-70 - Santosh G. Abraham, B. Ramakrishna Rau:
Efficient design space exploration in PICO. 71-79 - Prashant Arora, Rajesh K. Gupta:
Design and implementation of a hierarchical exception handling extension to systemC. 80-84 - Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee:
Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB. 85-93 - Benoît Dupont de Dinechin, François de Ferrière, Christophe Guillon, Artour Stoutchinin:
Code generator optimizations for the ST120 DSP-MCU core. 93-102 - Peng Yang, Dirk Desmet, Francky Catthoor, Diederik Verkest:
Dynamic scheduling of concurrent tasks with cost performance trade-off. 103-109 - Shige Wang, Kang G. Shin:
An architecture for embedded software integration using reusable components. 110-118 - B. Ramakrishna Rau:
The era of embedded computing. 119 - Hsien-Hsin S. Lee, Gary S. Tyson:
Region-based caching: an energy-delay efficient memory architecture for embedded processors. 120-127 - Tor M. Aamodt, Paul Chow:
Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation. 128-137 - Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Energy-oriented compiler optimizations for partitioned memory architectures. 138-147 - Yonghong Song, Yuan Lin:
Unroll-and-jam for imperfectly-nested loops in DSP applications. 148-156 - Subramanian Rajagopalan, Manish Vachharajani, Sharad Malik
:
Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. 157-164 - Afzal Malik, Bill Moyer, Dan Cermak:
A programmable unified cache architecture for embedded applications. 165-171 - Michael J. Schulte, Pablo I. Balzola, Jie Ruan, C. John Glossner:
Parallel saturating multioperand adders. 172-179 - Mohamed Shalan, Vincent John Mooney III:
A dynamic memory management unit for embedded real-time system-on-a-chip. 180-186 - Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky:
A first-step towards an architecture tuning methodology for low power. 187-192 - Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung:
Flexible instruction processors. 193-200
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