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ORCID28th DDECS 2025: Lyon, France
- 28th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2025, Lyon, France, May 5-7, 2025. IEEE 2025, ISBN 979-8-3315-2801-0
- Mounika Vaddeboina, Alper Yilmazer, Wolfgang Ecker:
Energy-Efficient Neural Network Inference through Golomb-Rice Compression of Activations for Edge Devices. 1-6 - Weiyan Zhang, Muhammad Hassan, Rolf Drechsler:
LLM-assisted Performance Estimation of Embedded Software on RISC-V Processors. 7-12 - Hussien Abdo, Jan Lappas, Mohammadreza Esmaeilpour, Christian Weis, Norbert Wehn:
Design of a Low-Power 4.3 Gb/s Transceiver Using Pre-computed Lookup Tables. 8-13 - Nicolò Bellarmino, Alberto Bosio, Riccardo Cantoro, Annachiara Ruospo, Ernesto Sánchez
:
DEAR-CNN: Data-Efficient Assessment of Resiliency in Convolutional Neural Networks. 13-18 - Anton Maidl, Abhoy Kole, Kamalika Datta, Jannis Stoppe, Rolf Drechsler:
Towards an Automated Debugging Approach for Fault Identification in Quantum Circuits. 19-24 - Till Schnittka, Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler:
River: Sneak Path Aware READ-based In-Memory Computing for 1T1M Memristive Crossbars. 31-36 - Mohammad Reza Heidari Iman, Sergio Vinagrero Gutierrez, Elena-Ioana Vatajelu, Giorgio Di Natale:
An Innovative Data Mining Technique for Automatic Anomaly Detection in Physical Unclonable Functions. 37-42 - Daniel Thirion, Jean-Marc Daveau, Valentin Egloff, David Hély, Vincent Beroulle, Philippe Roche:
Comparative Study of Safety and Security-Protected AES Designs. 43-48 - Mingqing Zhang, Alejandro Masrur:
Mitigating DoS Attacks on CAN: A Priority-Raise Approach and Its Timing Analysis. 49-54 - Mohammad Reza Heidari Iman, Giorgio Di Natale, Katell Morin-Allory:
A Survey on Automatic Assertion Miners. 55-60 - Elia Lazzeri, Matteo Colella, Gianluca Furano, Luca Cassano:
S4V: A Benchmark Suite of Transient Execution Attacks for RISC-V Processors. 61-67 - Francesco Gagliardi, Michele Dei:
Accuracy Enhancement of Resistor-String Digital-to-Analog Converters through Averaging Dynamic Element Matching. 74-79 - Róbert Ondica, David Maljar, Miroslav Potocný, Daniel Arbet, Viera Stopjaková:
Tunable Voltage Reference circuit in a standard 65nm CMOS technology. 80-85 - Gianluca Radi, Ares Tahiraga, Robert Kunzelmann, Ties Jan Henderikus Kluter, Wolfgang Ecker:
Implementation of Dynamic SISD-SIMD Integer Dividers. 86-91 - Andrea Costamagna, Xiaoqing Xu, Giovanni De Micheli, Dino Ruic:
Lazy Man's Resynthesis For Glitching-Aware Power Minimization. 92-98 - Christoph Hazott, Daniel Große:
Boosting SW Development Efficiency with Function Lifetime Diagrams. 99-104 - Claire Fenouillet-Béranger, Laurent Fesquet, Rihab Chouk, Gabriel Pares, Baudoin Martineau, Marie Claire Cyrille, Thierry Poiroux, Olivier Billoint, Dominique Noguet:
Ultra-Thin-Body and Buried Oxide FD-SOI next generation nodes and eNVM technologies for advanced IC design. 105-114 - Francesco Tosoni, Sara Vinco, Franco Fummi:
Modeling and Simulation of Thermal Faults in Batteries for Enhanced Safety. 115-118 - Amir Hossein Hadipour, Atousa Jafari, Muhammad Awais, Marco Platzner:
A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation. 119-122 - Obed M. Mogaka, Håkan Forsberg, Masoud Daneshtalab:
Bridging Quantization and Deployment: A Fixed-Point Workflow for FPGA Accelerators. 123-126 - Michal Zácek, Petr Fiser:
Controllability-Based Circuit Similarity Estimation. 127-130 - Sergiu-Mohamed Abed, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Gianluca De Lucia, Marco Lapegna, Matteo Sonza Reorda:
Analysis and Mitigation of Soft-errors in GPU-accelerated Hyperspectral Image Classifiers. 131-134 - Frank Wasinski, Werner Bonath, Ubbo Ricklefs, Michael Schwarz, Josef Börcsök:
Study of an OPTO-ASIC for a Functionally Safe Speed Sensor Using the Spatial Frequency Filter Method. 135-138 - Mario Barbareschi, Salvatore Barone, Alberto Bosio, Bastien Deveautour, Ali Piri, Marcello Traiola:
Automatic generation of input-aware approximate arithmetic circuits. 139-144 - Mahdi Taheri, Parth Patne, Natalia Cherezova, Ali Mahani, Christian Herglotz, Maksim Jenihhin:
RL-Agent-based Early-Exit DNN Architecture Search Framework. 145-148 - Maryam Rajabalipanah, Zahra Hojati, Zahra Jahanpeima, Zainalabedin Navabi:
Domain-Specific Design Abstraction with Emphasis on Neural Networks. 149-152 - Karl Aaron Rudkowski, Sallar Ahmadi-Pour, Rolf Drechsler:
CrosSym: Cross-Level Verification of SystemC Peripherals using Symbolic Execution. 153-156 - Quentin Milot, Mickaël Dardaillon, Daniel Ménard:
Stratified sampling: fast estimation of quantization effects on DNN. 157-160 - Michal Pinos, Jan Klhufek, Vojtech Mrazek, Lukás Sekanina:
Inference Energy Analysis in Context of Hardware-Aware NAS. 161-164 - Daniel Blokhin:
Duality and resonance in RLC-circuits. Exact formulas for phase, amplitude resonance and bandwidth. 165-168
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