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Zain Navabi
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2020 – today
- 2024
[j37]Nooshin Nosrati
, Zainalabedin Navabi:
Analysis and Enhancement of Resilience for LSTM Accelerators Using Residue-Based CEDs. IEEE Access 12: 52851-52866 (2024)- [j36]Alireza Nahvy, Zainalabedin Navabi:
Pico-Programmable Neurons to Reduce Computations for Deep Neural Network Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1216-1227 (2024) - [c166]Katayoon Basharkhah, Zainalabedin Navabi:
Event-Based Power Analysis Integrated with Timing Characterization and Logic Simulation. ISVLSI 2024: 684-688 - 2023
- [c165]Nooshin Nosrati, Zainalabedin Navabi:
A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators. DDECS 2023: 83-86 - [c164]Zahra Hojati, Zainalabedin Navabi:
A Low-Cost Combinational Approximate Multiplier. DDECS 2023: 136-139 - [c163]Mahboobe Sadeghipour Roodsari, Fatemeh Sheikhshoaei, Nicolò Maunero, Paolo Prinetto, Zain Navabi:
LiFi-CFI: Light-weight Fine-grained Hardware CFI Protection for RISC-V. DTTIS 2023: 1-6 - [c162]Katayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad-Javad Zare, Zainalabedin Navabi:
Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction. ETS 2023: 1-6 - [c161]Ebrahim Nouri, Nooshin Nosrati, Hanieh Totonchi Asl, Mozhgan Rezaie Manavand, Zainalabedin Navabi:
Multi-Level Fault Injection Methodology Using UVM-SystemC. EWDTS 2023: 1-6 - [c160]Negin Safari, Amirmahdi Joudi, Maryam Rajabalipanah, Zahra Jahanpeima, Hasan Sadeghzadeh, Zainalabedin Navabi:
HIRMA: High-Performance Implementation for RISC-V Microcontroller Applications. EWDTS 2023: 1-6 - 2022
- [c159]Nooshin Nosrati, Seyedeh Maryam Ghasemi, Mahboobe Sadeghipour Roodsari, Zainalabedin Navabi:
Concurrent Error Detection for LSTM Accelerators. ETS 2022: 1-2 - [c158]Nooshin Nosrati, Maksim Jenihhin, Zainalabedin Navabi:
MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors. IOLTS 2022: 1-5 - [c157]Mahboobe Sadeghipour Roodsari, Ebrahim Nouri, Fatemeh Sheikhshoaei, Paolo Prinetto, Zainalabedin Navabi:
A Secure Canary-Based Hardware Approach Against ROP. ITASEC 2022: 64-75 - [i5]Fatemeh Sheikh Shoaei, Alireza Nahvy, Zainalabedin Navabi:
Testable Array Multipliers for a Better Utilization of C-Testability and Bijectivity. CoRR abs/2201.11978 (2022) - 2021
- [c156]Nooshin Nosrati, Katayoon Basharkhah, Hanieh Totonchi Asl, Zahra Mahdavi, Zainalabedin Navabi:
Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester. DTIS 2021: 1-6 - [c155]Mohammad Rasoul Roshanshah, Katayoon Basharkhah, Zainalabedin Navabi:
Online Testing of a Row-Stationary Convolution Accelerator. ETS 2021: 1-2 - [c154]Maryam Rajabalipanah, Mahboobe Sadeghipour Roodsari, Zahra Jahanpeima, Gianluca Roascio, Paolo Prinetto, Zainalabedin Navabi:
AFTAB: A RISC-V Implementation with Configurable Gateways for Security. EWDTS 2021: 1-6 - [c153]Mahsa Akhsham, Zainalabedin Navabi:
Integrating an Interconnect BIST with Crosstalk Avoidance Hardware. IOLTS 2021: 1-6 - [c152]Mahboobe Sadeghipour Roodsari, Hanieh Totonchi Asl, Zainalabedin Navabi:
n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM Accelerator. ISVLSI 2021: 206-211 - 2020
- [j35]Mohammad Ebrahimi, Rezgar Sadeghi, Zainalabedin Navabi:
LUT Input Reordering to Reduce Aging Impact on FPGA LUTs. IEEE Trans. Computers 69(10): 1500-1506 (2020) - [j34]Mohammad Ebrahimi, Zainalabedin Navabi:
Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2976-2989 (2020) - [j33]Somayeh Sadeghi Kohan, Mehdi Kamal, Zainalabedin Navabi:
Self-Adjusting Monitor for Measuring Aging Rate and Advancement. IEEE Trans. Emerg. Top. Comput. 8(3): 627-641 (2020) - [c151]Mahboobe Sadeghipour Roodsari, Mohamad Ali Saber, Zainalabedin Navabi:
DiBA: n-Dimensional Bitslice Architecture for LSTM Implementation. DDECS 2020: 1-6 - [c150]Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Zainalabedin Navabi:
Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations. DDECS 2020: 1-4 - [c149]Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Zainalabedin Navabi:
Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator. DFT 2020: 1-4 - [c148]Rezgar Sadeghi, Zainalabedin Navabi:
Built-In Predictors for Dynamic Crosstalk Avoidance. ETS 2020: 1-6 - [c147]Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Zainalabedin Navabi:
ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links. VTS 2020: 1-6
2010 – 2019
- 2019
- [c146]Mahsa Akhsham, Atefesadat Seyedolhosseini, Zainalabedin Navabi:
Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme. ETS 2019: 1-2 - [c145]Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi:
Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling. ETS 2019: 1-6 - [c144]Samira Ahmadi Farsani, Katayoon Basharkhah, Amin Mohaghegh, Zainalabedin Navabi:
From Abstract Modeling of ADAS Applications to an Accelerator-based Hardware Realization. EWDTS 2019: 1-6 - [c143]Seyyede Maryam Ghasemy, Maryam Rajabalipanah, Saeideh Sarmadi, Zainalabedin Navabi:
SCOAP-based Directed Random Test Generation for Combinational Circuits. EWDTS 2019: 1-5 - [c142]Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Carna Zivkovic, Christoph Grimm, Zainalabedin Navabi:
Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment. EWDTS 2019: 1-5 - [c141]Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi:
An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. EWDTS 2019: 1-6 - [c140]Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Zainalabedin Navabi:
An ESL Environment for Modeling Electrical Interconnect Faults. ISVLSI 2019: 88-93 - 2018
- [j32]Reza Sharafinejad, Bijan Alizadeh, Zainalabedin Navabi:
Automatic Correction of Dynamic Power Management Architecture in Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 308-318 (2018) - [j31]Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi:
Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1845-1853 (2018) - [c139]Ramin Rezaeizadeh Rookerd, Somayeh Sadeghi Kohan, Zainalabedin Navabi:
Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. ACM Great Lakes Symposium on VLSI 2018: 33-38 - [c138]Somayeh Sadeghi Kohan, Arash Vafaei, Zainalabedin Navabi:
Near-Optimal Node Selection Procedure for Aging Monitor Placement. IOLTS 2018: 6-11 - 2017
- [j30]Zana Ghaderi, Mohammad Ebrahimi, Zainalabedin Navabi, Eli Bozorgzadeh, Nader Bagherzadeh:
SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs. IEEE Trans. Computers 66(5): 919-926 (2017) - [j29]Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi:
Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2059-2070 (2017) - [c137]Shaghayegh Vahdat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Zainalabedin Navabi:
TruncApp: A truncation-based approximate divider for energy efficient DSP applications. DATE 2017: 1635-1638 - [c136]Rasool Sharifi, Zainalabedin Navabi:
Online Profiling for cluster-specific variable rate refreshing in high-density DRAM systems. ETS 2017: 1-6 - [c135]Farzaneh Zokaee, Hossein Sabaghian Bidgoli, Vahid Janfaza, Payman Behnam, Zainalabedin Navabi:
A novel SAT-based ATPG approach for transition delay faults. HLDVT 2017: 17-22 - [c134]Hossein Sabaghian Bidgoli, Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi:
Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach. ISVLSI 2017: 545-550 - [i4]Elaheh Sadredini, Mohammadreza Najafi, Mahmood Fathy, Zainalabedin Navabi:
BILBO-friendly Hybrid BIST Architecture with Asymmetric Polynomial Reseeding. CoRR abs/1711.08458 (2017) - [i3]Elaheh Sadredini, Mohammad Hashem Haghbayan, Mahmood Fathy, Zainalabedin Navabi:
Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint. CoRR abs/1711.08974 (2017) - [i2]Elaheh Sadredini, Reza Rahimi, Paniz Foroutan, Mahmood Fathy, Zainalabedin Navabi:
An Improved Scheme for Pre-computed Patterns in Core-based SoC Architecture. CoRR abs/1711.08975 (2017) - 2016
- [j28]Arezoo Kamran, Zainalabedin Navabi:
Stochastic testing of processing cores in a many-core architecture. Integr. 55: 183-193 (2016) - [j27]Arezoo Kamran, Zainalabedin Navabi:
Self-Healing Many-Core Architecture: Analysis and Evaluation. VLSI Design 2016: 9767139:1-9767139:17 (2016) - [c133]Mohammad Ebrahimi, Zana Ghaderi, Eli Bozorgzadeh, Zain Navabi:
Path selection and sensor insertion flow for age monitoring in FPGAs. DATE 2016: 792-797 - [c132]Hamed Najafi Haghi, Mikhail M. Chupilko, Alexander S. Kamkin, Zainalabedin Navabi:
ESL design with RTL-verified predesigned abstract communication channels. EWDTS 2016: 1-7 - [c131]Maksim Jenihhin, Alexander Kamkin, Zainalabedin Navabi, Somayeh Sadeghi Kohan:
Universal mitigation of NBTI-induced aging by design randomization. EWDTS 2016: 1-5 - [c130]Elaheh Sadredini, Reza Rahimi, Paniz Foroutan, Mahmood Fathy, Zainalabedin Navabi:
An improved scheme for pre-computed patterns in core-based SoC architecture. EWDTS 2016: 1-6 - [c129]Morteza Soltani, Mohammad Ebrahimi, Zainalabedin Navabi:
Prolonging Lifetime of Non-volatile Last Level Caches with Cluster Mapping. ACM Great Lakes Symposium on VLSI 2016: 329-334 - [c128]Seyedeh Hanieh Hashemi, Reza Namazian, Zainalabedin Navabi:
Optimistic clock adjustment for preventing Better-than-worst-case violations. VLSI-SoC 2016: 1-6 - 2015
- [j26]Hasan Sohofi, Zainalabedin Navabi:
System-level assertions: approach for electronic system-level verification. IET Comput. Digit. Tech. 9(3): 142-152 (2015) - [j25]Mohammad Ansari, Hassan Afzali-Kusha, Behzad Ebrahimi, Zainalabedin Navabi, Ali Afzali-Kusha, Massoud Pedram:
A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies. Integr. 50: 91-106 (2015) - [j24]Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi:
Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition. IEEE Trans. Computers 64(6): 1579-1593 (2015) - [c127]Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Mohammad Fattah, Pasi Liljeberg, Juha Plosila, Zainalabedin Navabi, Hannu Tenhunen:
Power-aware online testing of manycore systems in the dark silicon era. DATE 2015: 435-440 - [c126]Mehran Goli, Amin Ghasemazar, Zainalabedin Navabi:
Application-specific power-aware mapping for reconfigurable NoC architectures. DTIS 2015: 1-6 - [c125]Rasoul Jafari, Elham Zahraei Salehi, Zain Navabi:
Utilizing NOPs for online deterministic testing of simple processing cores. DTIS 2015: 1-2 - [c124]Somayeh Sadeghi Kohan, Mehdi Kamal, John McNeil, Paolo Prinetto, Zain Navabi:
Online self adjusting progressive age monitoring of timing variations. DTIS 2015: 1-2 - [c123]Zainalabedin Navabi:
HDLs evolve as they affect design methodology for a higher abstraction and a better integration. DTIS 2015: 1 - [c122]Amirreza Nekooei, Zainalabedin Navabi:
Multi-valued logic test access mechanism for test time and power reduction. DTIS 2015: 1-6 - [c121]Somayeh Sadeghi Kohan, Arezoo Kamran, Farnaz Forooghifar, Zainalabedin Navabi:
Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. DTIS 2015: 1-6 - [c120]Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi:
Low power scheduling in high-level synthesis using dual-Vth library. ISQED 2015: 507-511 - [c119]Elmira Karimi, Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Mahmoud Tabandeh, Pasi Liljeberg, Zainalabedin Navabi:
Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model. MCSoC 2015: 283-288 - [c118]Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi:
Signature oriented model pruning to facilitate multi-threaded processors debugging. VTS 2015: 1-6 - 2014
- [j23]Mohammadreza Baharani, Hamid Noori, Mohammad Aliasgari, Zain Navabi:
High-level design space exploration of locally linear neuro-fuzzy models for embedded systems. Fuzzy Sets Syst. 253: 44-63 (2014) - [c117]Paniz Foroutan, Mehdi Kamal, Zainalabedin Navabi:
A heuristic path selection method for small delay defects test. DFT 2014: 252-257 - [c116]Shahrzad Keshavarz, Amirreza Nekooei, Zainalabedin Navabi:
Preemptive multi-bit IJTAG testing with reconfigurable infrastructure. DFT 2014: 293-298 - [c115]Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi:
Automatic correction of certain design errors using mutation technique. ETS 2014: 1-2 - [c114]Arezoo Kamran, Zainalabedin Navabi:
Homogeneous many-core processor system test distribution and execution mechanism. ETS 2014: 1-2 - [c113]Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi:
Improving polynomial datapath debugging with HEDs. ETS 2014: 1-6 - [c112]Marzieh Mohammadi, Somayeh Sadeghi Kohan, Nasser Masoumi, Zainalabedin Navabi:
An off-line MDSI interconnect BIST incorporated in BS 1149.1. ETS 2014: 1-2 - [c111]Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi:
RTL datapath optimization using system-level transformations. ISQED 2014: 309-316 - [c110]Hasan Sohofi, Zainalabedin Navabi:
Assertion-based verification for system-level designs. ISQED 2014: 582-588 - [c109]Farimah Farahmandi, Bijan Alizadeh, Zainalabedin Navabi:
Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits. ISVLSI 2014: 338-343 - [c108]Najmeh Farajipour Ghohroud, Zainalabedin Navabi:
Back-annotation of gate-level power properties into system level descriptions. NEWCAS 2014: 237-240 - [c107]Parastoo Kamranfar, Ali Shahabi, Ghazaleh Vazhbakht, Zainalabedin Navabi:
Configurable Systolic Matrix Multiplication. VLSID 2014: 336-341 - 2013
- [j22]Mohammad Mirzaei, Mahmoud Tabandeh, Bijan Alizadeh, Zainalabedin Navabi:
A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits. IEEE Des. Test 30(4): 49-59 (2013) - [c106]Payman Behnam, Hossein Sabaghian Bidgoli, Bijan Alizadeh, Kamyar Mohajerani, Zainalabedin Navabi:
A probabilistic approach for counterexample generation to aid design debugging. EWDTS 2013: 1-5 - [c105]Arezoo Kamran, Vahid Janfaza, Zainalabedin Navabi:
Extracting complete set of equations to analyze VHDL-AMS descriptions. EWDTS 2013: 1-4 - [c104]Somayeh Sadeghi Kohan, Shahrzad Keshavarz, Farzaneh Zokaee, Farimah Farahmandi, Zainalabedin Navabi:
A new structure for interconnect offline testing. EWDTS 2013: 1-5 - [c103]Arezoo Kamran, Zainalabedin Navabi:
Online periodic test mechanism for homogeneous many-core processors. VLSI-SoC 2013: 256-259 - [c102]Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören:
Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. VLSI-SoC 2013 - 2012
- [c101]Hossein Sabaghian Bidgoli, Majid Namaki-Shoushtari, Zainalabedin Navabi:
A Probabilistic and Constraint Based Approach for Low Power Test Generation. Asian Test Symposium 2012: 113-118 - [c100]M. H. Haghbayan, Saeed Safari, Zainalabedin Navabi:
Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST. DDECS 2012: 42-45 - [c99]Parisa Kabiri, Zainalabedin Navabi:
Effective RT-level software-based self-testing of embedded processor cores. DDECS 2012: 209-212 - [c98]Mohammadreza Najafi, Saeed Safari, Zainalabedin Navabi:
Soft Error Analysis on Communication Channels in On-Chip Communication Networks. DSD 2012: 852-857 - [c97]Reza Nakhjavani, Ali Shahabi, Saeed Safari, Zainalabedin Navabi:
A novel graceful degradable routing algorithm for 3D on-chip networks. INA-OCMC@HiPEAC 2012: 17-20 - [c96]Somayeh Sadeghi Kohan, Majid Namaki-Shoushtari, Fatemeh Javaheri, Zainalabedin Navabi:
BS 1149.1 extensions for an online interconnect fault detection and recovery. ITC 2012: 1-9 - [c95]Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi, Masahiro Fujita:
Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2m and algebraic techniques. MEMOCODE 2012: 65-74 - 2011
- [c94]Nastaran Nemati, Zainalabedin Navabi:
Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing. Asian Test Symposium 2011: 72-77 - [c93]Fatemeh Javaheri, Majid Namaki-Shoushtari, Parastoo Kamranfar, Zainalabedin Navabi:
Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware. Asian Test Symposium 2011: 114-119 - [c92]Behnam Khodabandeloo, Seyyed Alireza Hoseini, Sajjad Taheri, Mohammad Hashem Haghbayan, Mahmood Reza Babaei, Zainalabedin Navabi:
Online Test Macro Scheduling and Assignment in MPSoC Design. Asian Test Symposium 2011: 148-153 - [c91]Atieh Lotfi, Parisa Kabiri, Zainalabedin Navabi:
Configurable architecture for memory BIST. EWDTS 2011: 1-5 - 2010
- [j21]Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Zainalabedin Navabi:
EDXY - A low cost congestion-aware routing algorithm for network-on-chips. J. Syst. Archit. 56(7): 256-264 (2010) - [j20]Mohammad Reza Jamali, Masood Deh-Yadegari, Arash Arami, Caro Lucas, Zainalabedin Navabi:
Real-time embedded emotional controller. Neural Comput. Appl. 19(1): 13-19 (2010) - [c90]M. H. Haghbayan, Sara Karamati, Fatemeh Javaheri, Zainalabedin Navabi:
Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment. Asian Test Symposium 2010: 53-56 - [c89]S. Behdad Hosseini, Ali Shahabi, Hasan Sohofi, Zainalabedin Navabi:
A reconfigurable online BIST for combinational hardware using digital neural networks. ETS 2010: 139-144 - [c88]Fatemeh Javaheri, Zainalabedin Navabi:
ESL design methodology for architecture exploration. EWDTS 2010: 395-401 - [c87]Amirali Ghofrani, Sheis Abolma'ali, Zahra Najafi Haghi, Zainalabedin Navabi:
A TLM2.0 assertion library with centralized monitoring approach. EWDTS 2010: 402-406 - [c86]Arezoo Kamran, Nastaran Nemati, Somayeh Sadeghi Kohan, Zainalabedin Navabi:
Virtual tester development using HDL/PLI. EWDTS 2010: 412-415 - [c85]Arezoo Kamran, Mohammad Saeed Jahangiry, Zainalabedin Navabi:
Merit based directed random test generation (MDRTG) scheme for combinational circuits. EWDTS 2010: 416-419 - [c84]Niki Shakeri, Nastaran Nemati, Majid Nili Ahmadabadi, Zainalabedin Navabi:
Near optimal machine learning based random test generation. EWDTS 2010: 420-424 - [c83]Homa Alemzadeh, Marco Cimei, Paolo Prinetto, Zainalabedin Navabi:
Facilitating testability of TLM FIFO: SystemC implementations. EWDTS 2010: 428-431 - [c82]Homa Alemzadeh, Soheil Aminzadeh, Reihaneh Saberi, Zainalabedin Navabi:
Code optimization for enhancing SystemC simulation time. EWDTS 2010: 431-434 - [c81]Mohammad Hashem Haghbayan, Alireza Yazdanpanah, Sara Karamati, Ramyar Saeedi, Zainalabedin Navabi:
Generating test patterns for sequential circuits using random patterns by PLI functions. EWDTS 2010: 456-461 - [c80]Mohammad Hossein Sargolzaei, Mehdi Semsarzadeh, Mahmoud Reza Hashemi, Zainalabedin Navabi:
Low cost error tolerant motion estimation for H.264/AVC standard. EWDTS 2010: 461-465 - [c79]M. H. Haghbayan, Zainalabedin Navabi:
Architecture design and technical methodology for bus testing. EWDTS 2010: 504-509 - [c78]Amirali Ghofrani, Fatemeh Javaheri, Zainalabedin Navabi:
Assertion based verification in TLM. EWDTS 2010: 509-513 - [c77]Nastaran Nemati, Majid Namaki-Shoushtari, Zainalabedin Navabi:
A mixed HDL/PLI test package. EWDTS 2010: 518-523 - [c76]Ali Shahabi, S. Behdad Hosseini, Hasan Sohofi, Zainalabedin Navabi:
A partitioning approach to improve reconfigurable neuron-inspired online BIST. IOLTS 2010: 173-178 - [c75]Amirali Ghofrani, Fatemeh Javaheri, Saeed Safari, Zainalabedin Navabi:
Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization. SoC 2010: 111-114 - [c74]Sara Karamati, Zainalabedin Navabi:
Using context based methods for test data compression. ITC 2010: 809
2000 – 2009
- 2009
- [j19]Mohammad Reza Jamali, Arash Arami, Masood Deh-Yadegari, Caro Lucas, Zainalabedin Navabi:
Emotion on FPGA: Model driven approach. Expert Syst. Appl. 36(4): 7369-7378 (2009) - [j18]Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi:
Sign Bit Reduction Encoding For Low Power Applications. J. Signal Process. Syst. 57(3): 321-329 (2009) - [c73]Nastaran Nemati, Amirhossein Simjour, Amirali Ghofrani, Zainalabedin Navabi:
Optimizing Parametric BIST Using Bio-inspired Computing Algorithms. DFT 2009: 268-276 - 2008
- [j17]Naghmeh Karimi, Armin Alaghi, Mahshid Sedghi, Zainalabedin Navabi:
Online Network-on-Chip Switch Fault Detection and Diagnosis Using Functional Switch Faults. J. Univers. Comput. Sci. 14(22): 3716-3736 (2008) - [j16]Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi:
A Selective Trigger Scan Architecture for VLSI Testing. IEEE Trans. Computers 57(3): 316-328 (2008) - [c72]Pejman Lotfi-Kamran, Masoud Daneshtalab, Caro Lucas, Zainalabedin Navabi:
BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs. DATE 2008: 1408-1413 - [c71]Nadereh Hatami, Zainalabedin Navabi:
An advanced method for synthesizing TLM2-based interfaces. EWDTS 2008: 104-108 - [c70]Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi:
An IEEE 1500 compatible wrapper architecture for testing cores at transaction level. EWDTS 2008: 178-181 - [c69]Negin Mahani, Parnian Mokri, Zainalabedin Navabi:
System level hardware design and simulation with SystemAda. EWDTS 2008: 190-193 - [c68]Somayeh Malekshahi, Mahshid Sedghi, Zainalabedin Navabi:
Automating Hardware/Software partitioning using dependency Graph. EWDTS 2008: 196-199 - [c67]Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Mahmood Fathy, Zainalabedin Navabi:
Reliable NoC architecture utilizing a robust rerouting algorithm. EWDTS 2008: 200-203 - [c66]Najmeh Farajipour, S. Behdad Hosseini, Zainalabedin Navabi:
Utilizing HDL simulation engines for accelerating design and test processes. EWDTS 2008: 371-375 - [c65]Homa Alemzadeh, Zainalabedin Navabi, Stefano Di Carlo, Alberto Scionti, Paolo Prinetto:
Functional testing approaches for "BIFST-able" tlm_fifo. HLDVT 2008: 85-92 - [c64]Naghmeh Karimi, Soheil Aminzadeh, Saeed Safari, Zainalabedin Navabi:
A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing. IOLTS 2008: 173-174 - [c63]Fatemeh Refan, Homa Alemzadeh, Saeed Safari, Paolo Prinetto, Zainalabedin Navabi:
Reliability in Application Specific Mesh-Based NoC Architectures. IOLTS 2008: 207-212 - [c62]Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Zainalabedin Navabi:
NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structure. ITC 2008: 1 - [c61]Homa Alemzadeh, Stefano Di Carlo, Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi:
"Plug & Test" at System Level via Testable TLM Primitives. ITC 2008: 1-10 - [c60]Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi:
An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations. VLSI Design 2008: 409-414 - [c59]Pejman Lotfi-Kamran, Mehran Massoumi, Mohammad Mirzaei, Zainalabedin Navabi:
Enhanced TED: A New Data Structure for RTL Verification. VLSI Design 2008: 481-486 - [c58]Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, Zainalabedin Navabi:
Stall Power Reduction in Pipelined Architecture Processors. VLSI Design 2008: 541-546 - 2007
- [j15]Ali Shahabi, Nima Honarmand, Hasan Sohofi, Zainalabedin Navabi:
Degradable mesh-based on-chip networks using programmable routing tables. IEICE Electron. Express 4(10): 332-339 (2007) - [j14]Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio Lombardi, Zainalabedin Navabi:
Low overhead DFT using CDFG by modifying controller. IET Comput. Digit. Tech. 1(4): 322-333 (2007) - [j13]Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi:
Low test application time resource binding for behavioral synthesis. ACM Trans. Design Autom. Electr. Syst. 12(2): 16 (2007) - [c57]Majid Nabi, Hamid Shojaei, Siamak Mohammadi, Zainalabedin Navabi:
Optimized Assignment Coverage Computation in Formal Verification of Digital Systems. ATS 2007: 172-177 - [c56]Mahshid Sedghi, Armin Alaghi, Elnaz Koopahi, Zainalabedin Navabi:
An HDL-Based Platform for High Level NoC Switch Testing. ATS 2007: 453-458 - [c55]Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi:
Using the inter- and intra-switch regularity in NoC switch testing. DATE 2007: 361-366 - [c54]Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi:
A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. DDECS 2007: 247-250 - [c53]Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi:
Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode. DFT 2007: 21-30 - [c52]Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi:
On-Chip Verification of NoCs Using Assertion Processors. DSD 2007: 535-538 - [c51]Nima Honarmand, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi:
APDL: A Processor Description Language For Design Space Exploration of Embedded Processors. FDL 2007: 50-55 - [c50]Parisa Razaghi, Shahrzad Mirkhani, Zainalabedin Navabi:
A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library. FDL 2007: 171-176 - [c49]Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, Fabrizio Lombardi:
RT level reliability enhancement by constructing dynamic TMRS. ACM Great Lakes Symposium on VLSI 2007: 172-175 - [c48]Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi:
An Analytical Model for Reliability Evaluation of NoC Architectures. IOLTS 2007: 49-56 - [c47]Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale:
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. IOLTS 2007: 205-206 - [c46]Ali Shahabi, Nima Honarmand, Zainalabedin Navabi:
Programmable Routing Tables for Degradable Torus-Based Networks on Chips. ISCAS 2007: 1065-1068 - [c45]Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi:
A New Approach for Design and Verification of Transaction Level Models. ISCAS 2007: 3760-3763 - [c44]Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi:
A UML Based System Level Failure Rate Assessment Technique for SoC Designs. VTS 2007: 243-248 - [c43]Nima Honarmand, Ali Shahabi, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi:
High Level Synthesis of Degradable ASICs Using Virtual Binding. VTS 2007: 311-317 - [i1]Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi:
Simultaneous Reduction of Dynamic and Static Power in Scan Structures. CoRR abs/0710.4653 (2007) - 2006
- [j12]Ehsan Atoofian, Zainalabedin Navabi:
A Test Approach for Look-Up Table Based FPGAs. J. Comput. Sci. Technol. 21(1): 141-146 (2006) - [j11]Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi:
Scan-Based Structure with Reduced Static and Dynamic Power Consumption. J. Low Power Electron. 2(3): 477-487 (2006) - [c42]Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi:
NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm. ASAP 2006: 33-38 - [c41]Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi:
ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs. ATS 2006: 195-202 - [c40]Armin Alaghi, Mahnaz Sadoughi Yarandi, Zainalabedin Navabi:
An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing. ATS 2006: 293-298 - [c39]Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi:
A concurrent testing method for NoC switches. DATE 2006: 1171-1176 - [c38]Hadi Esmaeilzadeh, A. Moghimi, Eiman Ebrahimi, Caro Lucas, Zainalabedin Navabi, A. M. Fakhraie:
DCim++: a C++ library for object oriented hardware design and distributed simulation. ISCAS 2006 - [c37]Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi:
Low-power and low-latency cluster topology for local traffic NoCs. ISCAS 2006 - [c36]Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi:
Serial Bus Encoding for Low Power Application. SoC 2006: 1-4 - [c35]Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi:
An Optimized BIST Architecture for FPGA Look-Up Table Testing. ISVLSI 2006: 420-421 - [c34]Masood Deh-Yadegari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi:
A New Protocol Stack Model for Network on Chip. ISVLSI 2006: 440-441 - [c33]Masoud Daneshtalab, Ali Afzali-Kusha, Ashkan Sobhani, Zainalabedin Navabi, Mohammad D. Mottaghi, Omid Fatemi:
Ant colony based routing architecture for minimizing hot spots in NOCs. SBCCI 2006: 56-61 - [c32]Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi:
ByZFAD: a low switching activity architecture for shift-and-add multipliers. SBCCI 2006: 179-183 - 2005
- [b1]Zainalabedin Navabi:
Digital design and implementation with field programmable devices. Kluwer 2005, ISBN 978-1-4020-8011-1, pp. I-XVI, 1-293 - [j10]Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi:
Instruction-level test methodology for CPU core self-testing. ACM Trans. Design Autom. Electr. Syst. 10(4): 673-689 (2005) - [c31]Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi:
TED+: a data structure for microprocessor verification. ASP-DAC 2005: 567-572 - [c30]Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi:
ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing. Asian Test Symposium 2005: 236-241 - [c29]Shahrzad Mirkhani, Zainalabedin Navabi:
Enhancing Fault Simulation Performance by Dynamic Fault Clustering. Asian Test Symposium 2005: 278-283 - [c28]Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi:
Sign bit reduction encoding for low power applications. DAC 2005: 214-217 - [c27]Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi:
Simultaneous Reduction of Dynamic and Static Power in Scan Structures. DATE 2005: 846-851 - [c26]Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi:
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment. DFT 2005: 389-397 - [c25]Mostafa Naderi, Zainalabedin Navabi:
Combination of Assertion and HSAT Methods For Automated Test Vectors Generation. FDL 2005: 479-485 - [c24]Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi:
Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams. ISCAS (1) 2005: 424-427 - [c23]Mohammad Alisafaee, Safar Hatami, Ehsan Atoofian, Zainalabedin Navabi, Ali Afzali-Kusha:
A low-power scan-path architecture. ISCAS (5) 2005: 5278-5281 - [c22]Mohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram A. Riahi, Fabrizio Lombardi, Zainalabedin Navabi:
A Flow Graph Technique for DFT Controller Modification. SoCC 2005: 55-60 - [c21]Hamid Reza Ghasemi, Zainalabedin Navabi:
An Effective VHDL-AMS Simulation Algorithm with Event Partitioning. VLSI Design 2005: 762-767 - 2004
- [j9]Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin:
A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores. J. Electron. Test. 20(2): 155-168 (2004) - [j8]Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi:
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation. J. Electron. Test. 20(6): 575-589 (2004) - [j7]Farzin Karimi, Zainalabedin Navabi, Waleed Meleis, Fabrizio Lombardi:
Using data compression in automatic test equipment for system-on-chip testing. IEEE Trans. Instrum. Meas. 53(2): 308-317 (2004) - [c20]Bijan Alizadeh, Zainalabedin Navabi:
Property Checking based on Hierarchical Integer Equations. ACSD 2004: 26-35 - [c19]Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi:
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores. Asian Test Symposium 2004: 158-163 - [c18]Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi:
Instruction level test methodology for CPU core software-based self-testing. HLDVT 2004: 25-29 - [c17]Bijan Alizadeh, Zainalabedin Navabi:
Using Integer Equations to Check PSL Properties in RT Level Design. IWSOC 2004: 83-86 - 2003
- [c16]Ehsan Atoofian, Zainalabedin Navabi:
A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. Asian Test Symposium 2003: 84-89 - [c15]Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi:
The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology. Asian Test Symposium 2003: 274-277 - [c14]Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi:
Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment. Embedded Systems and Applications 2003: 139-143 - [c13]Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi:
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. DFT 2003: 352-360 - [c12]Elham Safi, Zohreh Karimi, Maghsoud Abbaspour, Zainalabedin Navabi:
Utilizing Various ADL Facets for Instruction Level CPU Test. MTV 2003: 38- - [c11]Morteza Fayyazi, David R. Kaeli, Zainalabedin Navabi:
Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching. PDPTA 2003: 819-823 - [c10]Elham Safi, Reihaneh Saberi, Zohreh Karimi, Zainalabedin Navabi:
Processor Testing Using an ADL Description and Genetic Algorithms. VLSI-SOC 2003: 186- - [c9]Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi:
Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. VLSI-SOC 2003: 215-220 - [c8]Ehsan Atoofian, Zainalabedin Navabi:
A Low Power BIST Architecture for FPGA Look-Up Table Testing. VLSI-SOC 2003: 394-397 - 2002
- [c7]Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi:
Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models. Asian Test Symposium 2002: 374- - [c6]Farzin Karimi, Waleed Meleis, Zainalabedin Navabi, Fabrizio Lombardi:
Data Compression for System-on-Chip Testing Using ATE. DFT 2002: 166-176 - 2001
- [c5]Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi:
Fault Simulation for VHDL Based Test Bench and BIST Evaluation. Asian Test Symposium 2001: 396- - [c4]Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi:
Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation. DATE 2001: 823 - [c3]Mohammad H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie:
An efficient BIST method for testing of embedded SRAMs. ISCAS (5) 2001: 73-76
1990 – 1999
- 1999
- [r1]Zainalabedin Navabi:
Hardware Description in Verilog. The VLSI Handbook 1999 - 1995
- [j6]Zainalabedin Navabi, Zahra Razavi:
A Transistor Level Link for VHDL Simulation of VLSI Circuits. Simul. 64(3): 185-197 (1995) - 1993
- [c2]Zainalabedin Navabi, Amirhooshang Hashemi, Massoud Eghtesad, Mankuan Michael Vai:
Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models. CHDL 1993: 569-586 - 1992
- [j5]Zainalabedin Navabi:
A high-level language for design and modeling of hardware. J. Syst. Softw. 18(1): 5-18 (1992) - 1991
- [j4]Zainalabedin Navabi:
Compiling gate RC models into a top level simulation model for rough timing analysis of VLSI circuits. Microprocess. Microsystems 15(6): 313-320 (1991) - [j3]Zainalabedin Navabi, Mehran Massoumi:
Investigating simulation of hardware at various levels of abstraction and timing back-annotation of dataflow descriptions. Simul. 57(5): 321-332 (1991)
1980 – 1989
- 1984
- [j2]Fredrick J. Hill, Zainalabedin Navabi, Chen H. Chiang, Duan-Ping Chen, Manzer Masud:
Hardware Compilation from an RTL to a Storage Logic Array Target. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(3): 208-217 (1984) - 1981
- [j1]Fredrick J. Hill, R. E. Swanson, Manzer Masud, Zainalabedin Navabi:
Structure Specification with a Procedural Hardware Description Language. IEEE Trans. Computers 30(2): 157-161 (1981)
1970 – 1979
- 1979
- [c1]Zainalabedin Navabi, Fredrick J. Hill:
Efficient simulation of AHPL. DAC 1979: 255-262
Coauthor Index
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