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ORCID14th FDL 2011: Oldenburg, Germany
- 2011 Forum on Specification & Design Languages, FDL 2011, Oldenburg, Germany, September 13-15, 2011. IEEE 2011, ISBN 978-1-4577-0763-6
- Sumit Adhikari, Christoph Grimm, Jan Haase:
Abstract modelling and estimation of a high performance Tobey's PGA. 1-6 - Ime J. Umoh, Tom J. Kazmierski:
VHDL-AMS model of a dual gate graphene FET. 1-5 - Mingyu Ma, Lars Hedrich, Christian Sporrer:
A machine-readable specification of analog circuits for integration into a validation flow. 1-8 - Laurence Pierre, Laila Damri:
Improvement of Assertion-Based Verification through the generation of proper test sequences. 1-8 - Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet, Alejandro Chagoya:
Does asynchronous technology bring robustness in synchronous circuit monitoring? 1-6 - Aurélien Ribon, Bertrand Le Gal, Christophe Jégo, Dominique Dallet:
Assertion support in high-level synthesis design flow. 1-8 - Ivan Shcherbakov, Christian Weis, Norbert Wehn:
Bringing C++ productivity to VHDL world: From language definition to a case study. 1-7 - Rauf Salimi Khaligh, Martin Radetzki:
A metamodel and semantics for transaction level modeling. 1-8 - Mike Gemunde, Jens Brandt, Klaus Schneider:
Schizophrenia and causality in the context of refined clocks. 1-8 - Sébastien Le Nours, Anthony Barreteau, Olivier Pasquier:
A generic execution model for efficient performance evaluation of system architectures at transaction level. 1-8 - Padma Iyenghar, Elke Pulvermüller, Clemens Westerkamp, Juergen Wuebbelmann:
Integrated model-based approach and test framework for embedded systems. 1-8 - Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda:
A UML based framework for efficient validation of TLM 2 models. 1-8 - Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Francesco Stefanni, Sara Vinco:
Efficient implementation and abstraction of systemc data types for fast simulation. 1-7 - Bastian Haetzer, Martin Radetzki:
A case study on message-based discrete event simulation for Transaction Level Modeling. 1-8 - Frank Poppen, Roland Koppe, Kim Grüttner, Axel Hahn:
Impact simulation of changes to development processes: An ESL case study. 1-6 - Fernando Herrera, Eugenio Villar:
A framework for the generation from UML/MARTE models of IPXACT HW platform descriptions for multi-level performance estimation. 1-8 - Gilberto Ochoa, El-Bay Bourennane, Ouassila Labbani, Kamel Messaoudi:
IP-XACT and marte based approach for partially reconfigurable systems-on-chip. 1-8 - Sebastian Offermann, Robert Wille, Rolf Drechsler:
Efficient realization of control logic in reversible circuits. 1-7 - Fernando Herrera, Eugenio Villar, Philipp A. Hartmann:
Systemc refinement of abstract adaptive processes for implementation into Dynamically Reconfigurable Hardware. 1-8 - Seyed-Hosein Attarzadeh-Niaki, Ingo Sander:
Semi-formal refinement of heterogeneous embedded systems by foreign model integration. 1-8 - Pablo González de Aledo Marugán, Javier Gonzalez Bayon, Pablo Sánchez Espeso:
Hardware performance estimation by dynamic scheduling. 1-6 - Jens Brandt, Mike Gemunde, Klaus Schneider, Sandeep K. Shukla, Jean-Pierre Talpin:
Integrating system descriptions by clocked guarded actions. 1-8 - Martin Streubühr, Rafael Rosales, Ralph Hasholzner, Christian Haubelt, Jürgen Teich:
ESL power and performance estimation for heterogeneous MPSOCS using SystemC. 1-8 - Marc Michael, Daniel Große, Rolf Drechsler:
Analyzing dependability measures at the Electronic System Level. 1-8 - Joseph Wenninger, Javier Moreno, Jan Haase, Christoph Grimm:
Designing low-power wireless sensor networks. 1-6 - Fabio Cenni, Serge Scotti, Emmanuel Simeu:
Behavioral modeling of a CMOS video sensor platform using systemc AMS/TLM. 1-6 - Mu Zhou, René van Leuken:
Systemc-AMS model of a dynamic large-scale satellite-based AIS-like network. 1-8
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