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ORCIDICFPT 2024: Sydney, Australia
- International Conference on Field Programmable Technology, ICFPT 2024, Sydney, Australia, December 10-12, 2024. IEEE 2024, ISBN 979-8-3315-2321-3
- Yiqing Mao, Yanxing Jin, Wai-Shing Luk, Lingli Wang:
HBMalloc: Dynamic Memory Management in High-Level Synthesis for FPGA HBM. 1-2 - Junyi Zhu, Boyan Han, Qingjie Lang, Dunbo Zhang, Ruoxi Wang, Li Shen:
Design Multi-Model Accelerators via Automatically Extracting Computational Graph Similarities. 1-2 - Alexandre Singer, Hang Yan, Guozheng Zhang, Mark C. Jeffrey
, Mirjana Stojilovic, Vaughn Betz:
Multiqueue-Based FPGA Routing: Relaxed A* Priority Ordering for Improved Parallelism. 1-9 - Dirk Koch, Myrtle Shah, Gavaskar Kanagara, Riadh Ben Abdelhamid, Nguyen Dao:
MPD - Multi-Project Die Sharing Enabled by an Embedded FPGA. 1-9 - Miyuru Thathsara, Damith Anhettigama, Siew-Kei Lam, Duvindu Piyasena:
Hardware-Efficient Homogenized Key-Point Selection for Visual SLAM. 1-2 - Akira Hyodo, Satoru Jimbo, Daiki Okonogi, Genta Inoue, Thiem Van Chu, Masato Motomura, Kazushi Kawamura:
A Parallel-Trial Double-Update Annealing Processor for Enabling Highly-Effective Solution Search of Constrained Combinatorial Optimization Problems. 1-9 - Gurshaant Malik, Nachiket Kapre:
GraphNoC: Graph Neural Networks for Application-Specific FPGA NoC Performance Prediction. 1-9 - Jiangnan Li, Zhengyi Zhang, Xuegong Zhou, Lingli Wang:
An MLIR-Based Compiler for Hardware Acceleration with Recursion Support: (PhD Forum Paper). 1-4 - Yuntao Han, He Li, Qiang Liu:
Efficient Table-Lookup Inference of Binarized Convolutions with Kernel-Level Binding on FPGA. 1-2 - Aoxiang Qin, Minghua Shen, Nong Xiao:
Resource Dependency-Aware Scheduling for High-Level Synthesis with GNN and SDC. 1-9 - Chris Keilbart, Lesley Shannon:
TableCache: An Open-Source, Configurable, Last-Level Cache for FPGA Systems. 1-10 - Hazem Taha, Ameer M. S. Abdelhadi:
HEPPO: Hardware-Efficient Proximal Policy Optimization a Universal Pipelined Architecture for Generalized Advantage Estimation. 1-9 - Huizhen Kuang, Lingli Wang:
Compass: A Collaborative HLS Design Space Exploration Framework via Graph Representation Learning and Ensemble Bayesian Optimization. 1-9 - Fahrican Kosar, Mirjana Stojilovic, Vaughn Betz:
Parallel FPGA Routing with On-The-Fly Net Decomposition. 1-9 - Haruhiko Hasegawa, Masayuki Shimoda, Hiroki Nakahara, Takefumi Miyoshi:
A Table Look-Up Based Quantum Simulation Accelerator on an FPGA. 1-2 - Jingwei Zhang, Jiyuan Pu, Hu Chen, Xiang Li, Meng Zhang:
TMM-DSE: Topology-Aware MLP-Mixer for QoR Prediction in HLS Design Space Exploration. 1-4 - Zenan Cui, Jingwei Zhang, Weijiang Tang, Hu Chen, Jiaqi Liu, Lizi Zhang, Meng Zhang:
Efficient DSP Packing Method for Neural Network Accelerator. 1-4 - Stewart Denholm, Wayne Luk:
Field-Programmable Dynamic Deep Learning. 1-2 - Xiang Li, Jingwei Zhang, Junhua Xiang, Yongming Wang, Peng Wang, Yanrong Wang, Feng Xu, Meng Zhang, An Jing:
A Hardware-Friendly Rotation Convolution Neural Network and its FPGA Implementation for Remote Sensing Scene Classification. 1-2 - Xingyu Tian, Geng Yang, Zhenman Fang:
FLUD: A Scalable and Configurable Systolic Array Design for LU Decomposition on FPGAs. 1-9 - Zongcheng Yue, Dongwei Yan, Longyu Ma, Chiu-Wing Sham:
Gradient-Aware Depth Sensitivity Scoring for Optimizing Neural Network Pruning: (PhD Forum Paper). 1-4 - Muhammad Sabih, Abrarul Karim, Jakob Wittmann, Frank Hannig, Jürgen Teich:
Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs. 1-9 - Jiayin Qin, Yuan Dai, Lingli Wang:
CGRA-HD: An Efficient Reconfigurable Accelerator for Hyperdimensional Computing: (PhD Forum Paper). 1-4 - Oluwole Jaiyeoba, Abdullah T. Mughrabi, Morteza Baradaran, Beenish Gul, Kevin Skadron:
Swift: A Multi-FPGA Framework for Scaling Up Accelerated Graph Analytics. 1-10 - Zhiqiang Que, Anyan Zhao, José Gabriel F. Coutinho, Ce Guo, Wayne Luk:
Optimizing DNN Accelerator Compression Using Tolerable Accuracy Loss. 1-2 - Piotr Wzorek, Kamil Jeziorek, Tomasz Kryjak, Andréa Pinna:
Increasing the Scalability of Graph Convolution for FPGA-Implemented Event-Based Vision: (PhD Forum Paper). 1-4 - Zhaoyang Han, Yicheng Qian, Michael Zink, Miriam Leeser:
Memory-Efficient Sketch Acceleration for Handling Large Network Flows on FPGAs. 1-9 - Christoph Berganski, Felix Jentzsch, Marco Platzner, Max Kuhmichel, Heiner Giefers:
FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers. 1-10 - Yunfei Xiang, Jincheng Yu, Yuanfan Xu, Yu Hu, Kaiyuan Guo, Yuhan Dong, Yu Wang:
Load Balanced Sparse Bundle Adjustment Accelerator for CNN-Based Visual-Inertial Odometry on FPGA. 1-2 - Arun Iyer, Nishant Pawar, Dinesh Gaitonde, Nanditha Rao:
Sensing Timing Margin Contingencies in the Programmable Fabric of FPGAs. 1-9 - Mousa Al-Qawasmi, Andy Gean Ye:
A Regression-Based Approach Towards Estimating the Area, Delay and Leakage Power of Synthesizable FPGA Tiles. 1-10 - Xizheng Li, Kaichuang Shi, Wai-Shing Luk, Hao Zhou, Lingli Wang:
FPGA Routing Optimization Based on Multi-Level MUX Architecture. 1-8 - Ehsan Kabir, M. D. Arafat Kabir, Austin R. J. Downey, Jason D. Bakos, David Andrews, Miaoqing Huang:
Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs. 1-2 - Hongda Zhou, Weilin Tao, Oliver Diessel, Cormac Purcell:
Accelerating RavÆn for Real-Time Satellite Image Change Detection. 1-2
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