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ORCID19. ACM Great Lakes Symposium on VLSI 2009: Boston Area, MA, USA
- Fabrizio Lombardi, Sanjukta Bhanja, Yehia Massoud, R. Iris Bahar:
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009. ACM 2009, ISBN 978-1-60558-522-2 - Massoud Pedram:
Green computing: reducing energy cost and carbon footprint of information processing systems. 1-2
VLSI design
- José Manuel Velasco
, David Atienza, Katzalin Olcoz:
Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems. 3-8 - Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
Contact merging algorithm for efficient substrate noise analysis in large scale circuits. 9-14 - Renatas Jakushokas, Eby G. Friedman:
Simultaneous shield and repeater insertion. 15-20 - Marco D. Santambrogio, Massimo Redaelli, Marco Maggioni:
Task graph scheduling for reconfigurable architectures driven by reconfigurations hiding and resources reuse. 21-26 - Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Safe clocking for the setup and hold timing constraints in datapath synthesis. 27-32
Low power
- Yoonjin Kim, Rabi N. Mahapatra:
Dynamic context management for low power coarse-grained reconfigurable architecture. 33-38 - Wan-Yu Lee, Iris Hui-Ru Jiang:
VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power. 39-44 - Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria:
An interconnect-aware delay model for dynamic voltage scaling in NM technologies. 45-50 - Bei Yu, Sheqin Dong, Satoshi Goto, Song Chen:
Voltage-island driven floorplanning considering level-shifter positions. 51-56 - Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas:
Design of novel CAM core cell structures for an efficient implementation of low power BCAM system. 57-62 - Kunal P. Ganeshpure, Ilia Polian, Sandip Kundu, Bernd Becker:
Reducing temperature variability by routing heat pipes. 63-68
Testing
- Suraj Sindia, Virendra Singh, Vishwani D. Agrawal:
Polynomial coefficient based DC testing of non-linear analog circuits. 69-74 - Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic:
MYGEN: automata-based on-line test generator for assertion-based verification. 75-80 - Brendan Mullane, Ciaran MacNamee, Vincent O'Brien, Thomas Fleischmann:
An on-chip solution for static ADC test and measurement. 81-86 - Giovanni Beltrame, Cristiana Bolchini, Antonio Miele:
Multi-level fault modeling for transaction-level specifications. 87-92 - Irith Pomeranz, Sudhakar M. Reddy:
Partitioned n-detection test generation. 93-98 - Jacob White:
Design tools for emerging technologies. 99-100
Poster session 1
- Syed Zafar Shazli, Mehdi Baradaran Tahoori:
Soft error rate computation in early design stages using boolean satisfiability. 101-104 - Irith Pomeranz, Sudhakar M. Reddy:
Definition and application of approximate necessary assignments. 105-108 - Yusuf Osmanlioglu, Yusuf Onur Koçberber, Oguz Ergin:
Reducing parity generation latency through input value aware circuits. 109-112 - Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper:
Multicast routing with dynamic packet fragmentation. 113-116 - Jue Wang, Beihua Ying, Yongpan Liu, Huazhong Yang, Hui Wang:
Energy efficient architecture of sensor network node based on compression accelerator. 117-120 - Theocharis Theocharides, Maria K. Michael, Marios M. Polycarpou, Ajit Dingankar:
Towards embedded runtime system level optimization for MPSoCs: on-chip task allocation. 121-124 - Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi, Luca Benini:
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip. 125-128 - Henrique Cota de Freitas, Philippe Olivier Alexandre Navaux:
On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers. 129-132 - Cheng-Hung Lin, Hsien-Sheng Hsiao:
Hierarchical state machine architecture for regular expression pattern matching. 133-136 - Michael Kadin, Sherief Reda, Augustus K. Uht:
Central vs. distributed dynamic thermal management for multi-core processors: which one is better? 137-140 - Cesare Ferri, R. Iris Bahar, Mirko Loghi, Massimo Poncino:
Energy-optimal synchronization primitives for single-chip multi-processors. 141-144 - Basab Datta, Wayne P. Burleson:
Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors. 145-148 - Balasubramanian Sethuraman, Ranga Vemuri:
A methodology for application-specific NoC architecture generation in a dynamic task structure environment. 149-152 - Mehdi Baradaran Tahoori:
BISM: built-in self map for hybrid crossbar nano-architectures. 153-156 - Harika Manem, Garrett S. Rose:
The effects of logic partitioning in a majority logic based CMOS-NANO FPGA. 157-160 - Aarti Choudhary, Sandip Kundu:
A process variation tolerant self-compensating FinFET based sense amplifier design. 161-164 - Vikas Kaushal, Quentin Diduck, Martin Margala:
Study of leakage current mechanisms in ballistic deflection transistors. 165-168 - Karthik Duraisami, Enrico Macii, Massimo Poncino:
Using soft-edge flip-flops to compensate NBTI-induced delay degradation. 169-172 - Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler:
Contradictory antecedent debugging in bounded model checking. 173-176 - MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature. 177-180 - Yongji Jiang, Garrett S. Rose:
A dual-MOSFET equivalent resistor thermal sensor. 181-184
Physical level optimization
- Ali Jahanian, Morteza Saheb Zamani:
Improved performance and yield with chip master planning design methodology. 185-190 - Renshen Wang, Chung-Kuan Cheng:
Octilinear redistributive routing in bump arrays. 191-196 - Bo-Zhou Chen, Hung-Ming Chen, Li-Da Huang, Po-Cheng Pan:
A stochastic-based efficient critical area extractor on OpenAccess platform. 197-202 - Raghuram Srinivasan, Harold W. Carter:
A taylor series methodology for analyzing the effects of process variation on circuit operation. 203-208 - Jing Li, Bo Yang, Xiaochuan Hu, Qing Dong, Shigetoshi Nakatake:
STI stress aware placement optimization based on geometric programming. 209-214
VLSI circuits
- Ahmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia Di:
Glitch-free design for multi-threshold CMOS NCL circuits. 215-220 - Bin Zhang:
Online circuit reliability monitoring. 221-226 - Kelageri Nagaraj, Sandip Kundu:
Process variation mitigation via post silicon clock tuning. 227-232 - Mahta Haghi, Jeff Draper:
The effect of design parameters on single-event upset sensitivity of MOS current mode logic. 233-238 - Samed Maltabas, Martin Margala, Ugur Çilingiroglu:
Varicap threshold logic. 239-244
Emerging technology and post-CMOS
- Qi Wu, Jian-Qiang Lu, Kenneth Rose, Tong Zhang:
Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systems. 245-250 - Roto Le, Sherief Reda, R. Iris Bahar:
High-performance, cost-effective heterogeneous 3D FPGA architectures. 251-256 - Renshen Wang, Chung-Kuan Cheng:
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design. 257-262 - Vasilis F. Pavlidis, Giovanni De Micheli:
Power distribution paths in 3-D ICS. 263-268 - Shinya Kubota, Minoru Watanabe:
A nine-context programmable optically reconfigurable gate array with semiconductor lasers. 269-274 - Rajeev K. Dokania, Alyssa B. Apsel:
Analysis of challenges for on-chip optical interconnects. 275-280 - Eby G. Friedman:
Design challenges in high performance three-dimensional circuits. 281-282 - Pinaki Mazumder:
Disruptive technologies and neurally-inspired architectures. 283-284
Low power
- Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman:
Power efficient tree-based crosslinks for skew reduction. 285-290 - Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud:
Dual-threshold pass-transistor logic design. 291-296 - Colin J. Ihrig, Gerold Joseph Dhanabalan, Alex K. Jones:
A low-power CMOS thyristor based delay element with programmability extensions. 297-302 - Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos:
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO. 303-308 - Khawla Alzoubi, Daniel G. Saab, Massood Tabib-Azar:
Complementary nano-electromechanical switches for ultra-low power embedded processors. 309-314
System- and architectural-level optimization
- Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja:
A reconfigurable stochastic architecture for highly reliable computing. 315-320 - Chetan Murthy, Prabhat Mishra:
Bitmask-based control word compression for NISC architectures. 321-326 - Taemin Kim, Xun Liu:
Better than optimum?: register reduction using idle pipelined functional units. 327-332 - Andrea Calimera, Enrico Macii, Massimo Poncino:
NBTI-aware sleep transistor design for reliable power-gating. 333-338 - Di Wang, Vyas Venkataraman, Zhen Wang, Wei Qin, Hangsheng Wang, Mrinal Bose, Jayanta Bhadra:
Accelerating multi-party scheduling for transaction-level modeling. 339-344
Logic verification and optimization
- Yibin Chen, Sean Safarpour, Andreas G. Veneris, João Marques-Silva:
Spatial and temporal design debug using partial MaxSAT. 345-350 - Taiga Takata, Yusuke Matsunaga:
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. 351-356 - Jeff L. Cobb, Kanupriya Gulati, Sunil P. Khatri:
Robust window-based multi-node technology-independent logic minimization. 357-362 - David Bañeres, Jordi Cortadella, Michael Kishinevsky:
Timing-driven N-way decomposition. 363-368 - Mingjing Chen, Alex Orailoglu:
Deflecting crosstalk by routing reconsideration through refined signal correlation estimation. 369-374 - Wolfgang Porod:
Computing with field-coupled nanomagnets. 375-376
Poster session 2
- Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu:
Buffer design and optimization for lut-based structured ASIC design styles. 377-380 - Masa-Aki Fukase, Atsuko Yokoyama, Tomoaki Sato:
A ubiquitous processor embedded with progressive cipher pipelines. 381-384 - Pratik J. Shah, Jiang Hu:
Impact of lithography-friendly circuit layout. 385-388 - Marshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma:
A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects. 389-392 - Jin Cui, Douglas L. Maskell:
Dynamic thermal-aware scheduling on chip multiprocessor for soft real-time system. 393-396 - Yung-Chih Chen, Chun-Yao Wang:
Enhancing SAT-based sequential depth computation by pruning search space. 397-400 - Jin-Tai Yan, Zhi-Wei Chen:
RDL pre-assignment routing for flip-chip designs. 401-404 - Zhu Zhou, Dharmin Parikh, Pradnyesh Gudadhe, Arunabha Sen:
A novel mechanism to dynamically switch speed and accuracy in systemC based transaction level models. 405-408 - Jin-Tai Yan, Zhi-Wei Chen:
Redundant wire insertion for yield improvement. 409-412 - Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake:
Incremental buffer insertion and module resizing algorithm using geometric programming. 413-416 - Hong-Zu Chou, I-Hui Lin, Ching-Sung Yang, Kai-Hui Chang, Sy-Yen Kuo:
Enhancing bug hunting using high-level symbolic simulation. 417-420 - Dario Cozzi, Claudia Farè, Alessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices. 421-424 - Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, Patrick Schaumont:
Physical unclonable function and true random number generator: a compact and scalable implementation. 425-428 - Yanjie Peng, Andrew G. Klein, Xinming Huang:
Design of a maximum-likelihood detector for cooperative communications in intersymbol interference channels. 429-432 - Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala:
A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic. 433-436 - Yifei Luo, Gang Chen, Kuan Zhou:
A picosecond TDC architecture for multiphase PLLs. 437-440 - Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri:
Low power and high performance sram design using bank-based selective forward body bias. 441-444
VLSI design
- Yang Sun, Joseph R. Cavallaro:
High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm. 445-450 - Nariman Moezzi Madani, William Rhett Davis:
High-throughput low-complexity MIMO detector based on K-best algorithm. 451-456 - Josef B. Spjut, Andrew E. Kensler, Erik Brunvand:
Hardware-accelerated gradient noise for graphics. 457-462 - Yiqing Huang, Qin Liu, Satoshi Goto, Takeshi Ikenaga:
Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application. 463-468 - Ling Wang, Jianwen Zhang, Xiaoqing Yang, Dongxin Wen:
Router with centralized buffer for network-on-chip. 469-474
VLSI circuits
- Imran Ahmed, Cheran M. Vithanage:
Dynamic reconfiguration approach for high speed turbo decoding using circular rings. 475-480 - Yang Liu, Ashok Kumar Srivastava, Yao Xu:
A switchable PLL frequency synthesizer and hot carrier effects. 481-486 - Spandana Remarsu, Sandip Kundu:
On process variation tolerant low cost thermal sensor design in 32nm CMOS technology. 487-492 - Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello:
New performance/power/area efficient, reliable full adder design. 493-498 - Shu Li, Tong Zhang:
Improving multi-level NAND flash memory storage reliability using concatenated TCM-BCH coding. 499-504
Testing
- Reshma C. Jumani, Niraj Bharatkumar Jain, Virendra Singh, Kewal K. Saluja:
DX-compactor: distributed X-compaction for SoCs. 505-510 - Mohammad Hossein Neishaburi, Zeljko Zilic:
Reliability aware NoC router architecture using input channel buffer sharing. 511-516 - Zhen Chen, Dong Xiang, Boxue Yin:
A power-effective scan architecture using scan flip-flops clustering and post-generation filling. 517-522 - Irith Pomeranz, Sudhakar M. Reddy:
State persistence: a property for guiding test generation. 523-528 - Alodeep Sanyal, Abhisek Pan, Sandip Kundu:
A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits. 529-534
Tutorials
- Mohamad Sawan:
Intracortical wireless microsystems for biosensing and neurostimulation. 535-536 - Michael S. Shur:
Terahertz sensing technology. 537-538 - Nader Engheta:
Circuits with light at the nanoscale: meta-nanocircuits and metactronics. 539-540
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