default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID22nd ICPP 1993: Syracuse University, NY, USA - Volume 1
- C. Y. Roger Chen, P. Bruce Berra:
Proceedings of the 1993 International Conference on Parallel Processing, Syracuse University, NY, USA, August 16-20, 1993. Volume I: Architecture. CRC Press 1993, ISBN 0-8493-8984-4
Cache Memory (I)
- Anant Agarwal, David A. Kranz, Venkat Natarajan:
Automatic Partitioning of Parallel Loops for Cache-Coherent Multiprocessors. 2-11 - Jih-Kwon Peir, Kimming So, Ju-Ho Tang:
Techniques to Enhance Cache Performance Across Parallel Program Sections. 12-19 - Tzi-cker Chiueh:
A Generational Algorithm to Multiprocessor Cache Coherence. 20-24 - Nathalie Drach, André Seznec:
Semi-Unified Caches. 25-28
Processor and Communication Architecture
- Weijia Shang, Benjamin W. Wah:
Dependence Analysis and Architecture Design for Bit-Level Algorithms. 30-38 - Danny Cohen, Gregory G. Finn, Robert E. Felderman, Annette L. DeSchon:
ATOMIC: A Low-Cost, Very-High-Speed, Local Communication Architecture. 39-46 - Terence M. Potter, Hsiao-chen Chung, Chuan-lin Wu:
Reconfigurable Branch Processing Strategy in Super-Scalar Microprocessors. 47-50 - Daejoon Hwang, Seung Ho Cho, Y. D. Kim, Sangyong Han:
Exploiting Spatial and Temporal Parallelism in the Multithreaded Node Architecture Implemented on Superscalar RISC Processors. 51-54
Memory
- Fredrik Dahlgren, Michel Dubois, Per Stenström:
Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors. 56-63 - Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab:
Assigning Sites fto Redundant Clusters in a Distributed Storage System. 64-71 - Franck Cappello, Jean-Luc Béchennec, Franck Delaplace, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble:
Balanced Distributed Memory Parallel Computers. 72-76 - Honda Shing, Lionel M. Ni:
A Novel Approach to the Design of Scalable Shared-Memory Multiprocessors. 77-81
Graph_Theoretic Interconnection Structures (I)
- C. P. Ravikumar, A. Kuchlous, G. Manimaran:
Incomplete Star Graph: An Economical Fault-tolerant Interconnection Network. 83-90 - Shahram Latifi, Marcelo M. de Azevedo, Nader Bagherzadeh:
The Star Connected Cycles: A Fixed-Degree Network for Parallel Processing. 91-95 - Nian-Feng Tzeng:
Empirical Evaluation of Incomplete Hypercube Systems. 96-99 - Jyh-Charn Liu, Hung-ju Lee:
A Distributed Multicast Algorithm for Hypercube Multicomputers. 100-104 - Kathy J. Liszka, Kenneth E. Batcher:
A Generalized Bitonic Sorting Network. 105-108
Hypercube
- Prasant Mohapatra, Chansu Yu, Chita R. Das, Jong Kim:
A Lazy Scheduling Scheme for Improving Hypercube Performance. 110-117 - Debendra Das Sharma, Dhiraj K. Pradhan:
Fast and Efficient Strategies for Cubic and Non-Cubic Allocation in Hypercube Multiprocessors. 118-127 - Arif Ghafoor:
Random Routing of Tasks in Hypercube Architectures. 128-131 - Yeimkuan Chang, Laxmi N. Bhuyan:
Fault Tolerant Subcube Allocation in Hypercubes. 132-136
Architecture (I)
- Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab:
Performance of Redundant Disk Array Organizations in Transaction Processing Environments. 138-145 - Thomas J. Cloonan, Gaylord W. Richards:
The Chuted-Banyan (Canyan) Network: An Efficient Distribution Network for Growable Packet Switching Based on Free-Space Digital Optics. 146-153 - D. Scott Wills, Matthias Grossglauser:
A Scalable Optical Interconnection Network for Fine-Grain Parallel Architectures. 154-157 - Omkar M. Dighe, Ramachandran Vaidyanathan, Si-Qing Zheng:
Bus-Based Tree Structures for Efficient Parallel Computation. 158-161
Cache Memory (II)
- Ching-Farn Eric Wu, Yarsun Hsu, Yew-Huey Liu:
Efficient Stack Simulation for Shared Memory Set-Associative Multiprocessor Caches. 163-170 - Luis Barriga, Rassul Ayani:
Parallel Cache Simulation on Multiprocessor Workstations. 171-174 - Soon Myoung Chung, Longxue Li:
A Chained-Directory Cache Coherence Protocol for Multiprocessors. 175-179 - Olivier Temam, Christine Fricker, William Jalby:
Evaluating the Impact of Cache Interferences on Numerical Codes. 180-183 - Yung-Chin Chen, Alexander V. Veidenbaum:
Performance Evaluation of Memory Caches in Multiprocessors. 184-187
Performance Evaluation
- A. J. Field, Peter G. Harrison
:
Transmission Times in Buffered Full-Crossbar Communication Networks With Cyclic Arbitration. 189-196 - Athar B. Tayyab, Jon G. Kuhl:
Experimental Validation of a Performance Model for Simple Layered Task Systems. 197-201 - Todd C. Marek, Edward W. Davis:
Performance Evaluation of SIMD Processor Architectures Using Pairwise Multiplier Recoding. 202-205 - Earl Hokens, Ahmed Louri:
Performance Considerations Relating to the Design of Interconnection Networks for Multiprocessing Systems. 206-209 - Prasant Mohapatra, Chita R. Das:
A Queuing Model for Finite-Buffered Multistage Interconnection Networks. 210-213 - Samir M. Koriem, Lalit M. Patnaik:
Composite Performance and Reliability Analysis for Hypercube Systems. 214-217
Distributed Systems and Architecture
- Jaehyung Yang, Ishfaq Ahmad, Arif Ghafoor:
Estimation of Execution times on Heterogeneous Supercomputer Architectures. 219-226 - Chien-Chun Su, Kang G. Shin:
Adaptive Deadlock-Free Routing in Multicomputers Using Only One Extra Virtual Channel. 227-231 - Matthew I. Frank, Mary K. Vernon:
A Hybrid Shared Memory/Message Passing Parallel Machine. 232-236 - Umakishore Ramachandran, Gautam Shah, Ravi Kumar, Jeyakumar Muthukumarasamy:
Scalability Study of the KSR-1. 237-240 - Sanjay Ranka, Jhy-Chun Wang, Manoj Kumar:
Personalized Communication Avoiding Node Contention on Distributed Memory Systems. 241-244
Memory and Disks
- Shalini Yajnik, Niraj K. Jha:
Design of Algorithm-Based Fault Tolerant Systems With In-System Checks. 246-253 - Mazin S. Yousif, Chita R. Das, Matthew Thazhuthaveetil:
A Cache Coherence Protocol for MIN-Based Multprocessors With Limited Inclusion. 254-257 - Dannie Durand, Thierry Montaut, Lionel Kervella, William Jalby:
Impact of Memory Contention on Dynamic Scheduling on NUMA Multiprocessors. 258-262 - John A. Chandy, Prithviraj Banerjee:
Reliability Evalutaion of Disk Array Architectures. 263-267 - De-Lei Lee:
Prime-Way Interleaved Memory. 268-272
Routing Algorithms and Ring, Bus Structures
- Mu-Cheng Wang, Howard Jay Siegel, Mark A. Nichols, Seth Abraham:
Reducing the Effect of Hot Spots by Using a Multipath Network. 274-281 - Massimo Maresca, Hungwen Li, Pierpaolo Baglietto:
Hardware Suport for Fast Reconfigurability in Processor Arrays. 282-289 - Sameer M. Bataineh, Te-Yu Hsiung, Thomas G. Robertazzi:
Closed Form Solutions for Bus and Tree Networks of Processors Load Sharing A Divisible Job. 290-293 - Xiaola Lin, Philip K. McKinley, Lionel M. Ni:
The Message Flow Model for Routing in Wormhole-Routed Networks. 294-297
Graph Theoretic Interconnection Structures (II)
- W. J. Hsu, Moon-Jung Chung:
Generalized Fibonacci Cubes. 299-302 - Yashovardhan R. Potlapalli, Dharma P. Agrawal:
HMIN: A New Method for Hierarchical Interconnection of Processors. 303-306 - Peter Thomas Breznay, Mario Alberto López:
Tightly Connected Hierarchical Interconnection Networks for Parallel Processors. 307-310 - Sabine R. Öhring, Sajal K. Das:
The Folded Petersen Network: A New Communication-Efficient Multiprocessor Topology. 311-314 - Ronald Fernandes, Arkady Kanevsky:
Hierarchical WK-Recursive Topologies for Multicomputer Systems. 315-318 - Ronald Fernandes, Arkady Kanevsky:
Substructure Allocation in Recursive Interconnection Networks. 319-322
Architecture (II)
- R. Ananthanarayanan, Mustaque Ahamad, Richard J. LeBlanc:
Coherence, Synchronization and State-sharing in Distributed Shared-memory Applications. 324-331 - Prince Kohli, Gil Neiger, Mustaque Ahamad:
A Characterization of Scalable Shared Memories. 332-335 - Yoshikuni Okawa, Yasukazu Toteno, Bi Kai:
Real-Time Control of a Pipelined Multicomputer for the Relational Database Join Operation. 336-339 - Fabrizio Baiardi, Mehdi Jazayeri:
P3M: A Virtual Machine Approach to Massively Parallel Computing. 340-344 - Kian-Lee Tan, Hongjun Lu:
Pipeline Processing of Multi-Way Join Queries in Shared-Memory Systems. 345-348 - Howard Jay Siegel:
Panel: In Search of a Universal (But Useful) Model of a Parallel Computation. 349-350
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-05 22:22 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
