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ORCID32nd ISCA 2005: Madison, Wisconsin, USA
- 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA. IEEE Computer Society 2005, ISBN 978-0-7695-2270-8
Session 1: Security
- Ruby B. Lee, Peter C. S. Kwan, John Patrick McGregor, Jeffrey S. Dwoskin, Zhenghong Wang:
Architecture for Protecting Critical Secrets in Microprocessors. 2-13 - Weidong Shi, Hsien-Hsin S. Lee, Mrinmoy Ghosh, Chenghuai Lu, Alexandra Boldyreva:
High Efficiency Counter Mode Security Architecture via Prediction and Precomputation. 14-24 - G. Edward Suh
, Charles W. O'Donnell, Ishan Sachdev, Srinivas Devadas:
Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions. 25-36
Session 2a: Interacting with Disks and Networks
- Sudhanva Gurumurthi, Anand Sivasubramaniam, Vivek K. Natarajan:
Disk Drive Roadmap from the Thermal Perspective: A Case for Dynamic Thermal Management. 38-49 - Ram Huggahalli, Ravi R. Iyer, Scott Tetrick:
Direct Cache Access for High Bandwidth Network I/O. 50-59 - Haryadi S. Gunawi, Nitin Agrawal, Andrea C. Arpaci-Dusseau, Remzi H. Arpaci-Dusseau, Jiri Schindler:
Deconstructing Commodity Storage Clusters. 60-71
Session 2b: Memory Compression and Renamer Optimizations
- Magnus Ekman, Per Stenström:
A Robust Main-Memory Compression Scheme. 74-85 - Brian Fahs, Todd M. Rafacz, Sanjay J. Patel, Steven S. Lumetta:
Continuous Optimization. 86-97 - Vlad Petric, Tingting Sha, Amir Roth:
RENO - A Rename-Based Instruction Optimizer. 98-109
Session 3a: Specialized Processors
- Lin Tan, Timothy Sherwood:
A High Throughput String Matching Architecture for Intrusion Detection and Prevention. 112-122 - Florin Baboescu, Dean M. Tullsen, Grigore Rosu, Sumeet Singh:
A Tree Based Router Search Engine Architecture with Single Port Memories. 123-133 - Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai:
An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems. 134-145
Session 3b: Detecting Faults
- George A. Reis, Jonathan Chang, Neil Vachharajani, Ram Rangan, David I. August, Shubhendu S. Mukherjee:
Design and Evaluation of Hybrid Fault-Detection Systems. 148-159 - Ethan Schuchman, T. N. Vijaykumar:
Rescue: A Microarchitecture for Testability and Defect Tolerance. 160-171 - Mohamed A. Gomaa, T. N. Vijaykumar:
Opportunistic Transient-Fault Detection. 172-183
Session 4a: Quantum Computing and Very Low Power
- Steven Balensiefer, Lucas Kreger-Stickles, Mark Oskin:
An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures. 186-196 - Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David T. Blaauw:
Energy Optimization of Subthreshold-Voltage Sensor Network Processors. 197-207 - Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu-Yeon Wei, David M. Brooks:
An Ultra Low Power System Architecture for Sensor Network Applications. 208-219
Session 4b: Coherence
- Thomas F. Wenisch, Stephen Somogyi, Nikolaos Hardavellas, Jangwoo Kim, Anastassia Ailamaki, Babak Falsafi:
Temporal Streaming of Shared Memory. 222-233 - Andreas Moshovos:
RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence. 234-245 - Jason F. Cantin, Mikko H. Lipasti, James E. Smith:
Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking. 246-257
Session 5a: Applying Compilers and Debugging Support
- Stephen Hines, Joshua Green, Gary S. Tyson, David B. Whalley:
Improving Program Efficiency by Packing Instructions into Registers. 260-271 - Nathan Clark, Jason A. Blome, Michael L. Chu, Scott A. Mahlke, Stuart Biles, Krisztián Flautner:
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors. 272-283 - Satish Narayanasamy, Gilles Pokam, Brad Calder:
BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging. 284-295
Session 5b: Power
- Murali Annavaram, Ed Grochowski, John Paul Shen:
Mitigating Amdahl's Law through EPI Throttling. 298-309 - Emil Talpes, Diana Marculescu:
Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines. 310-321 - Vlad Petric, Amir Roth:
Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection. 322-333
Session 6a: Chip Multiprocessor Memory Hierarchies
- Michael Zhang, Krste Asanovic:
Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors. 336-345 - Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishnan Rajamony:
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors. 346-356 - Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar:
Optimizing Replication, Communication, and Capacity Allocation in CMPs. 357-368
Session 6b: Runahead and Branch Prediction
- Onur Mutlu, Hyesoon Kim, Yale N. Patt:
Techniques for Efficient Processing in Runahead Execution Engines. 370-381 - Daniel A. Jiménez:
Piecewise Linear Branch Prediction. 382-393 - André Seznec:
Analysis of the O-GEometric History Length Branch Predictor. 394-405
Session 7a: Interconnection Networks
- Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen:
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling. 408-419 - John Kim, William J. Dally, Brian Towles, Amit K. Gupta:
Microarchitecture of a High-Radix Router. 420-431 - Daeho Seo, Akif Ali, Won-Taek Lim, Nauman Rafique, Mithuna Thottethodi:
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks. 432-443
Session 7b: Load and Store Queues
- Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan, Konrad K. Lai:
Scalable Load and Store Processing in Latency Tolerant Processors. 446-457 - Amir Roth:
Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization. 458-468 - Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería:
Store Buffer Design in First-Level Multibanked Data Caches. 469-480
Session 8a: Multiprocessor Issues
- Albert Meixner, Daniel J. Sorin:
Dynamic Verification of Sequential Consistency. 482-493 - Ravi Rajwar, Maurice Herlihy, Konrad K. Lai:
Virtualizing Transactional Memory. 494-505 - Saisanthosh Balakrishnan, Ravi Rajwar, Michael Upton, Konrad K. Lai:
The Impact of Performance Asymmetry in Emerging Multicore Architectures. 506-517
Session 8b: Reliability and a Cache Organization
- Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers:
Exploiting Structural Duplication for Lifetime Reliability Enhancement. 520-531 - Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan:
Computing Architectural Vulnerability Factors for Address-Based Structures. 532-543 - Moinuddin K. Qureshi, David Thompson, Yale N. Patt:
The V-Way Cache: Demand Based Associativity via Global Replacement. 544-555
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