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2020 – today
- 2022
[j2]Michael B. Sullivan
, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler:
Characterizing and Mitigating Soft Errors in GPU DRAM. IEEE Micro 42(4): 69-77 (2022)- 2021
- [c9]Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler:
Characterizing and Mitigating Soft Errors in GPU DRAM. MICRO 2021: 641-653 - 2020
- [c8]Richard Bramley, Yanxiang Huang, Guangshan Duan, Nirmal R. Saxena, Paul Racunas:
On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors. ITC 2020: 1-10 - [i1]Siva Kumar Sastry Hari, Paolo Rech, Timothy Tsai, Mark Stephenson, Arslan Zulfiqar, Michael B. Sullivan, Philip P. Shirvani, Paul Racunas, Joel S. Emer, Stephen W. Keckler:
Estimating Silent Data Corruption Rates Using a Two-Level Model. CoRR abs/2005.01445 (2020)
2010 – 2019
- 2019
- [c7]Atieh Lotfi, Saurabh Hukerikar, Keshav Balasubramanian, Paul Racunas, Nirmal R. Saxena, Richard Bramley, Yanxiang Huang:
Resiliency of automotive object detection networks on GPU architectures. ITC 2019: 1-9 - 2018
- [c6]Atieh Lotfi, Nirmal R. Saxena, Richard Bramley, Paul Racunas, Philip P. Shirvani:
Low Overhead Tag Error Mitigation for GPU Architectures. DSN 2018: 314-321 - 2015
- [c5]Steven Raasch, Arijit Biswas, Jon Stephan, Paul Racunas, Joel S. Emer:
A fast and accurate analytical technique to compute the AVF of sequential bits in a processor. MICRO 2015: 738-749
2000 – 2009
- 2008
- [j1]Arijit Biswas, Paul Racunas, Joel S. Emer, Shubhendu S. Mukherjee:
Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal. IEEE Comput. Archit. Lett. 7(1): 21-24 (2008) - 2007
- [c4]Paul Racunas, Kypros Constantinides, Srilatha Manne, Shubhendu S. Mukherjee:
Perturbation-based Fault Screening. HPCA 2007: 169-180 - 2005
- [c3]Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan:
Computing Architectural Vulnerability Factors for Address-Based Structures. ISCA 2005: 532-543 - 2003
- [c2]Paul Racunas, Yale N. Patt:
Partitioned first-level cache design for clustered microarchitectures. ICS 2003: 22-31
1990 – 1999
- 1997
- [c1]Jared Stark, Paul Racunas, Yale N. Patt:
Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order. MICRO 1997: 34-43
Coauthor Index
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