Google
Google Scholar
Semantic Scholar
MS Academic
CiteSeerX
ORCIDMoinuddin K. Qureshi
Person information
- affiliation: Georgia Institute of Technology, Atlanta GA, USA
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2020
[c61]Sanjay Kariyappa, Moinuddin K. Qureshi:
Defending Against Model Stealing Attacks With Adaptive Misinformation. CVPR 2020: 767-775- [i12]Poulami Das, Christopher A. Pattison, Srilatha Manne, Douglas M. Carmean, Krysta M. Svore, Moinuddin K. Qureshi, Nicolas Delfosse:
A Scalable Decoder Micro-architecture for Fault-Tolerant Quantum Computing. CoRR abs/2001.06598 (2020) - [i11]Sanjay Kariyappa, Atul Prakash, Moinuddin K. Qureshi:
MAZE: Data-Free Model Stealing Attack Using Zeroth-Order Gradient Estimation. CoRR abs/2005.03161 (2020) - [i10]Gururaj Saileshwar, Moinuddin K. Qureshi:
MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design. CoRR abs/2009.09090 (2020)
2010 – 2019
- 2019
- [j9]Moinuddin K. Qureshi:
With New Memories Come New Challenges. IEEE Micro 39(1): 52-53 (2019) - [c60]Swamit S. Tannu, Moinuddin K. Qureshi:
Not All Qubits Are Created Equal: A Case for Variability-Aware Policies for NISQ-Era Quantum Computers. ASPLOS 2019: 987-999 - [c59]Swamit S. Tannu, Poulami Das, Michael L. Lewis, Robert F. Krick, Douglas M. Carmean, Moinuddin K. Qureshi:
A case for superconducting accelerators. CF 2019: 67-75 - [c58]Prashant J. Nair, Bahar Asgari, Moinuddin K. Qureshi:
SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM. DSN 2019: 388-400 - [c57]Vinson Young, Sanjay Kariyappa, Moinuddin K. Qureshi:
Enabling Transparent Memory-Compression for Commodity Memory Systems. HPCA 2019: 570-581 - [c56]Vinson Young, Moinuddin K. Qureshi:
To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches. ICCD 2019: 119-128 - [c55]Vinson Young, Zeshan A. Chishti, Moinuddin K. Qureshi:
TicToc: Enabling Bandwidth-Efficient DRAM Caching for Both Hits and Misses in Hybrid Memory Systems. ICCD 2019: 341-349 - [c54]Moinuddin K. Qureshi:
New attacks and defense for encrypted-address cache. ISCA 2019: 360-371 - [c53]Gururaj Saileshwar, Moinuddin K. Qureshi:
CleanupSpec: An "Undo" Approach to Safe Speculation. MICRO 2019: 73-86 - [c52]Swamit S. Tannu, Moinuddin K. Qureshi:
Ensemble of Diverse Mappings: Improving Reliability of Quantum Computers by Orchestrating Dissimilar Mistakes. MICRO 2019: 253-265 - [c51]Swamit S. Tannu, Moinuddin K. Qureshi:
Mitigating Measurement Errors in Quantum Computers by Exploiting State-Dependent Bias. MICRO 2019: 279-290 - [c50]Poulami Das, Swamit S. Tannu, Prashant J. Nair, Moinuddin K. Qureshi:
A Case for Multi-Programming Quantum Computers. MICRO 2019: 291-303 - [i9]Sanjay Kariyappa, Moinuddin K. Qureshi:
Improving Adversarial Robustness of Ensembles with Diversity Training. CoRR abs/1901.09981 (2019) - [i8]Swamit S. Tannu, Poulami Das, Michael L. Lewis, Robert F. Krick, Douglas M. Carmean, Moinuddin K. Qureshi:
A Case for Superconducting Accelerators. CoRR abs/1902.04641 (2019) - [i7]Gururaj Saileshwar, Moinuddin K. Qureshi:
Lookout for Zombies: Mitigating Flush+Reload Attack on Shared Caches by Monitoring Invalidated Lines. CoRR abs/1906.02362 (2019) - [i6]Vinson Young, Moinuddin K. Qureshi:
To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches. CoRR abs/1907.02167 (2019) - [i5]Vinson Young, Zeshan Chishti, Moinuddin K. Qureshi:
TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems. CoRR abs/1907.02184 (2019) - [i4]Sanjay Kariyappa, Moinuddin K. Qureshi:
Defending Against Model Stealing Attacks with Adaptive Misinformation. CoRR abs/1911.07100 (2019) - 2018
- [c49]Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, Moinuddin K. Qureshi:
SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories. HPCA 2018: 454-465 - [c48]Vinson Young, Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction. ISCA 2018: 328-339 - [c47]Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, José A. Joao, Moinuddin K. Qureshi:
Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories. MICRO 2018: 416-427 - [c46]Moinuddin K. Qureshi:
CEASER: Mitigating Conflict-Based Cache Attacks via Encrypted-Address and Remapping. MICRO 2018: 775-787 - [i3]Kevin K. Chang, Prashant J. Nair, Saugata Ghose, Donghyuk Lee, Moinuddin K. Qureshi, Onur Mutlu:
LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency. CoRR abs/1805.03184 (2018) - [i2]Swamit S. Tannu, Moinuddin K. Qureshi:
A Case for Variability-Aware Policies for NISQ-Era Quantum Computers. CoRR abs/1805.10224 (2018) - [i1]Vinson Young, Sanjay Kariyappa, Moinuddin K. Qureshi:
CRAM: Efficient Hardware-Based Memory Compression for Bandwidth Enhancement. CoRR abs/1807.07685 (2018) - 2017
- [j8]Aamer Jaleel, Moinuddin K. Qureshi:
Top Picks from the 2016 Computer Architecture Conferences. IEEE Micro 37(3): 6-11 (2017) - [c45]Jian Huang, Jun Xu, Xinyu Xing, Peng Liu, Moinuddin K. Qureshi:
FlashGuard: Leveraging Intrinsic Flash Properties to Defend Against Encryption Ransomware. CCS 2017: 2231-2244 - [c44]Jian Huang, Anirudh Badam, Laura Caulfield, Suman Nath, Sudipta Sengupta, Bikash Sharma, Moinuddin K. Qureshi:
FlashBlox: Achieving Both Performance Isolation and Uniform Lifetime for Virtualized SSDs. FAST 2017: 375-390 - [c43]Vinson Young, Prashant J. Nair, Moinuddin K. Qureshi:
DICE: Compressing DRAM Caches for Bandwidth and Capacity. ISCA 2017: 627-638 - [c42]Swamit S. Tannu, Douglas M. Carmean, Moinuddin K. Qureshi:
Cryogenic-DRAM based memory system for scalable quantum computers: a feasibility study. MEMSYS 2017: 189-195 - [c41]Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
BATMAN: techniques for maximizing system bandwidth of memory systems with stacked-DRAM. MEMSYS 2017: 268-280 - [c40]Swamit S. Tannu, Zachary A. Myers, Prashant J. Nair, Douglas M. Carmean, Moinuddin K. Qureshi:
Taming the instruction bandwidth of quantum computers via hardware-managed error correction. MICRO 2017: 679-691 - 2016
- [j7]Prashant J. Nair
, David A. Roberts, Moinuddin K. Qureshi:
FaultSim: A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems. ACM Trans. Archit. Code Optim. 12(4): 44:1-44:24 (2016) - [j6]Prashant J. Nair, David A. Roberts, Moinuddin K. Qureshi:
Citadel: Efficiently Protecting Stacked Memory from TSV and Large Granularity Failures. ACM Trans. Archit. Code Optim. 12(4): 49:1-49:24 (2016) - [c39]Sudarsun Kannan, Moinuddin K. Qureshi, Ada Gavrilovska, Karsten Schwan:
Energy Aware Persistence: Reducing Energy Overheads of Memory-based Persistence in NVMs. PACT 2016: 165-177 - [c38]Kevin K. Chang, Prashant J. Nair, Donghyuk Lee, Saugata Ghose, Moinuddin K. Qureshi, Onur Mutlu:
Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM. HPCA 2016: 568-580 - [c37]Prashant J. Nair, Vilas Sridharan, Moinuddin K. Qureshi:
XED: Exposing On-Die Error Detection Information for Strong Memory Reliability. ISCA 2016: 341-353 - [c36]Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
CANDY: Enabling coherent DRAM caches for multi-node systems. MICRO 2016: 35:1-35:13 - [c35]Jian Huang, Moinuddin K. Qureshi, Karsten Schwan:
An Evolutionary Study of Linux Memory Management for Fun and Profit. USENIX Annual Technical Conference 2016: 465-478 - 2015
- [j5]Dae-Hyun Kim, Prashant J. Nair, Moinuddin K. Qureshi:
Architectural Support for Mitigating Row Hammering in DRAM Memories. IEEE Comput. Archit. Lett. 14(1): 9-12 (2015) - [c34]Vinson Young, Prashant J. Nair, Moinuddin K. Qureshi:
DEUCE: Write-Efficient Encryption for Non-Volatile Memories. ASPLOS 2015: 33-44 - [c33]Chia-Chen Chou, Prashant J. Nair, Moinuddin K. Qureshi:
Reducing Refresh Power in Mobile Devices with Morphable ECC. DSN 2015: 355-366 - [c32]Moinuddin K. Qureshi, Dae-Hyun Kim, Samira Manabi Khan, Prashant J. Nair, Onur Mutlu:
AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems. DSN 2015: 427-437 - [c31]Prashant J. Nair, Chia-Chen Chou, Bipin Rajendran, Moinuddin K. Qureshi:
Reducing read latency of phase change memory via early read and Turbo Read. HPCA 2015: 309-319 - [c30]Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches. ISCA 2015: 198-210 - [c29]Jian Huang, Anirudh Badam, Moinuddin K. Qureshi, Karsten Schwan:
Unified address translation for memory-mapped SSDs with FlashMap. ISCA 2015: 580-591 - 2014
- [j4]Jian Huang, Karsten Schwan, Moinuddin K. Qureshi:
NVRAM-aware Logging in Transaction Systems. Proc. VLDB Endow. 8(4): 389-400 (2014) - [j3]Prashant J. Nair, Chia-Chen Chou, Moinuddin K. Qureshi:
Refresh pausing in DRAM memory systems. ACM Trans. Archit. Code Optim. 11(1): 10:1-10:26 (2014) - [c28]Nagakishore Jammula, Moinuddin K. Qureshi, Ada Gavrilovska, Jongman Kim:
Balancing context switch penalty and response time with elastic time slicing. HiPC 2014: 1-10 - [c27]Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache. MICRO 2014: 1-12 - [c26]Prashant J. Nair, David A. Roberts, Moinuddin K. Qureshi:
Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures. MICRO 2014: 51-62 - 2013
- [c25]Moinuddin K. Qureshi, Zeshan Chishti:
Operating SECDED-based caches at ultra-low voltage with FLAIR. DSN 2013: 1-11 - [c24]Prashant J. Nair, Chia-Chen Chou, Moinuddin K. Qureshi:
A case for Refresh Pausing in DRAM memory systems. HPCA 2013: 627-638 - [c23]Prashant J. Nair, Dae-Hyun Kim, Moinuddin K. Qureshi:
ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates. ISCA 2013: 72-83 - [c22]Moinuddin K. Qureshi:
Embedded tutorial - Emerging memory technologies: What it means for computer system designers. VLSI Design 2013 - 2012
- [c21]Jaewoong Sim, Jaekyu Lee, Moinuddin K. Qureshi, Hyesoon Kim:
FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion. ISCA 2012: 321-332 - [c20]Moinuddin K. Qureshi, Michele Franceschini, Ashish Jagmohan, Luis A. Lastras:
PreSET: Improving performance of phase change memories by exploiting asymmetry in write times. ISCA 2012: 380-391 - [c19]Moinuddin K. Qureshi, Gabriel H. Loh:
Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design. MICRO 2012: 235-246 - 2011
- [b1]Moinuddin K. Qureshi, Sudhanva Gurumurthi, Bipin Rajendran:
Phase Change Memory: From Devices to Systems. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2011 - [c18]Moinuddin K. Qureshi, André Seznec, Luis A. Lastras, Michele Franceschini:
Practical and secure PCM systems by online detection of malicious write streams. HPCA 2011: 478-489 - [c17]Moinuddin K. Qureshi:
Pay-As-You-Go: low-overhead hard-error correction for phase change memories. MICRO 2011: 318-328 - 2010
- [j2]M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt:
Accelerating Critical Section Execution with Asymmetric Multicore Architectures. IEEE Micro 30(1): 60-70 (2010) - [c16]M. Aater Suleman, Moinuddin K. Qureshi, Khubaib, Yale N. Patt:
Feedback-directed pipeline parallelism. PACT 2010: 147-156 - [c15]Moinuddin K. Qureshi, Michele Franceschini, Luis Alfonso Lastras-Montaño:
Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing. HPCA 2010: 1-11 - [c14]Moinuddin K. Qureshi, Michele Franceschini, Luis Alfonso Lastras-Montaño, John P. Karidis:
Morphable memory system: a robust architecture for exploiting multi-level phase change memories. ISCA 2010: 153-162
2000 – 2009
- 2009
- [c13]M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt:
Accelerating critical section execution with asymmetric multi-core architectures. ASPLOS 2009: 253-264 - [c12]Moinuddin K. Qureshi:
Adaptive Spill-Receive for robust high-performance caching in CMPs. HPCA 2009: 45-54 - [c11]Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers:
Scalable high performance main memory system using phase-change memory technology. ISCA 2009: 24-33 - [c10]Moinuddin K. Qureshi, John P. Karidis, Michele Franceschini, Vijayalakshmi Srinivasan, Luis A. Lastras, Bülent Abali:
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling. MICRO 2009: 14-23 - [c9]Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos:
A tagless coherence directory. MICRO 2009: 423-434 - 2008
- [j1]Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer:
Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching. IEEE Micro 28(1): 91-98 (2008) - [c8]Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer:
Adaptive insertion policies for managing shared caches. PACT 2008: 208-219 - [c7]M. Aater Suleman, Moinuddin K. Qureshi, Yale N. Patt:
Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs. ASPLOS 2008: 277-286 - 2007
- [c6]Moinuddin K. Qureshi, M. Aater Suleman, Yale N. Patt:
Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines. HPCA 2007: 250-259 - [c5]Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer:
Adaptive insertion policies for high performance caching. ISCA 2007: 381-391 - 2006
- [c4]Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt:
A Case for MLP-Aware Cache Replacement. ISCA 2006: 167-178 - [c3]Moinuddin K. Qureshi, Yale N. Patt:
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches. MICRO 2006: 423-432 - 2005
- [c2]Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt:
Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors. DSN 2005: 434-443 - [c1]Moinuddin K. Qureshi, David Thompson, Yale N. Patt:
The V-Way Cache: Demand Based Associativity via Global Replacement. ISCA 2005: 544-555
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
load content from web.archive.org
Privacy notice: By enabling the option above, your browser will contact the API of web.archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
Tweets on dblp homepage
Show tweets from 
on the dblp homepage.
Privacy notice: By enabling the option above, your browser will contact twitter.com and twimg.com to load tweets curated by our Twitter account. At the same time, Twitter will persistently store several cookies with your web browser. While we did signal Twitter to not track our users by setting the "dnt" flag, we do not have any control over how Twitter uses your data. So please proceed with care and consider checking the Twitter privacy policy.
last updated on 2020-11-11 21:55 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
the dblp computer science bibliography is funded by:
