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ORCID35th ISCA 2008: Beijing, China
- 35th International Symposium on Computer Architecture (ISCA 2008), June 21-25, 2008, Beijing, China. IEEE Computer Society 2008, ISBN 978-0-7695-3174-8
Novel Microarchitectures - Part I
- Francis Tseng, Yale N. Patt:
Achieving Out-of-Order Performance with Almost In-Order Complexity. 3-12 - Mayank Agarwal, Nitin Navale, Kshitiz Malik, Matthew I. Frank:
Fetch-Criticality Reduction through Control Independence. 13-24 - Miquel Pericàs, Adrián Cristal
, Francisco J. Cazorla, Rubén González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero:
A Two-Level Load/Store Queue Based on Execution Locality. 25-36
Novel Memory Systems
- Engin Ipek, Onur Mutlu, José F. Martínez, Rich Caruana:
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach. 39-50 - Shyamkumar Thoziyoor, Jung Ho Ahn, Matteo Monchiero, Jay B. Brockman, Norman P. Jouppi:
A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies. 51-62 - Onur Mutlu, Thomas Moscibroda:
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems. 63-74
Interconnect Networks - Part I
- John Kim, William J. Dally, Steve Scott, Dennis Abts:
Technology-Driven, Highly-Scalable Dragonfly Topology. 77-88 - Jae W. Lee, Man Cheuk Ng, Krste Asanovic:
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks. 89-100 - Martha Mercaldi Kim, John D. Davis, Mark Oskin, Todd M. Austin:
Polymorphic On-Chip Networks. 101-112
Transactional Memory
- Lee Baugh, Naveen Neelakantam, Craig B. Zilles:
Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory. 115-126 - Jayaram Bobba, Neelam Goyal, Mark D. Hill, Michael M. Swift, David A. Wood:
TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory. 127-138 - Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. Scott:
Flexible Decoupled Transactional Memory Support. 139-150
Emergent Technology
- Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn:
Corona: System Implications of Emerging Nanophotonic Technology. 153-164 - Lucas Kreger-Stickles, Mark Oskin:
Microcoded Architectures for Ion-Tap Quantum Computers. 165-176 - Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz:
Running a Quantum Circuit at the Speed of Data. 177-188
Novel Microarchitectures - Part II
- Xiaoyao Liang, Gu-Yeon Wei, David M. Brooks:
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency. 191-202 - Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu:
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. 203-214 - Franziska Roesner, Doug Burger, Stephen W. Keckler:
Counting Dependence Predictors. 215-226
Interconnect Networks - Part II
- Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti:
Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support. 229-240 - Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri:
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures. 241-250 - Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das:
MIRA: A Multi-layered On-Chip Interconnect Router Architecture. 251-261
Debugging Parallel Programs
- Derek Hower, Mark D. Hill:
Rerun: Exploiting Episodes for Lightweight Memory Race Recording. 265-276 - Brandon Lucia, Joseph Devietti, Karin Strauss, Luis Ceze:
Atom-Aid: Detecting and Surviving Atomicity Violations. 277-288 - Pablo Montesinos, Luis Ceze, Josep Torrellas:
DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Effciently. 289-300
System Architecture and I/O
- Sriram Sankar, Sudhanva Gurumurthi, Mircea R. Stan:
Intra-disk Parallelism: An Idea Whose Time Has Come. 303-314 - Kevin T. Lim, Parthasarathy Ranganathan, Jichuan Chang, Chandrakant D. Patel, Trevor N. Mudge, Steven K. Reinhardt:
Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments. 315-326 - Taeho Kgil, David Roberts, Trevor N. Mudge:
Improving NAND Flash Based Disk Caches. 327-338
Reliability
- Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers:
Online Estimation of Architectural Vulnerability Factor for Soft Errors. 341-352 - Jeonghee Shin, Victor V. Zyuban, Pradip Bose, Timothy Mark Pinkston:
A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime. 353-362 - Radu Teodorescu, Josep Torrellas:
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors. 363-374
Application Acceleration
- Shimin Chen, Michael Kozuch, Theodoros Strigkos, Babak Falsafi, Phillip B. Gibbons, Todd C. Mowry, Vijaya Ramachandran, Olatunji Ruwase, Michael P. Ryan, Evangelos Vlachos:
Flexible Hardware Acceleration for Instruction-Grain Program Monitoring. 377-388 - Nathan Clark, Amir Hormati, Scott A. Mahlke:
VEAL: Virtualized Execution Accelerator for Loops. 389-400 - Haibo Chen, Xi Wu, Liwei Yuan, Binyu Zang, Pen-Chung Yew, Frederic T. Chong:
From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware. 401-412
Performance Evaluation
- Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero:
Software-Controlled Priority Characterization of POWER5 Processor. 415-426 - Alex Shye, Berkin Özisikyilmaz, Arindam Mallik, Gokhan Memik, Peter A. Dinda, Robert P. Dick, Alok N. Choudhary:
Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction. 427-438
Multi-core/Many-core Design
- Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Yen-Kuang Chen, Jatin Chhugani, Christopher J. Hughes, Changkyu Kim, Victor W. Lee, Anthony D. Nguyen:
Atomic Vector Operations on Chip Multiprocessors. 441-452 - Gabriel H. Loh:
3D-Stacked Memory Architectures for Multi-core Processors. 453-464
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