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ORCIDISSS 1995: Cannes, France
- Pierre G. Paulin, Farhad Mavaddat:
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France. ACM 1995, ISBN 0-89791-771-5 - Ti-Yen Yen, Wayne H. Wolf:
Sensitivity-driven co-synthesis of distributed embedded systems. 4-9 - Jay K. Adams, Donald E. Thomas:
Multiple-process behavioral synthesis for mixed hardware-software systems. 10-15 - Jan Madsen
, Bjarne Hald:
An approach to interface synthesis. 16-21 - Pai H. Chou, Ross B. Ortega, Gaetano Borriello:
The Chinook hardware/software co-synthesis system. 22-27 - Frank Vahid, Daniel D. Gajski:
Clustering for improved system-level functional partitioning. 28-35 - Guido Araujo, Sharad Malik:
Optimal code generation for embedded memory non-homogeneous register architectures. 36-41 - David J. Kolson, Alexandru Nicolau, Nikil D. Dutt, Ken Kennedy:
Optimal register assignment to loops for embedded code generation. 42-47 - Filip Thoen, Marco Cornero, Gert Goossens, Hugo De Man:
Real-time multi-tasking in software synthesis for information processing systems. 48-53 - Rainer Leupers, Peter Marwedel:
Time-constrained code compaction for DSPs. 54-59 - Clifford Liem, Pierre G. Paulin, Marco Cornero, Ahmed Amine Jerraya:
Industrial experience using rule-driven retargetable code generation for multimedia applications. 60-68 - Joseph Sifakis:
Real-time systems specification and verification. 69 - Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man:
Synthesis of pipelined DSP accelerators with dynamic scheduling. 72-77 - Samit Chaudhuri, Stephen A. Blythe, Robert A. Walker:
An exact methodology for scheduling in a 3D design space. 78-83 - Frank Vahid:
Procedure exlining: a transformation for improved system and behavioral synthesis. 84-89 - Herman Schmit, Donald E. Thomas:
Array mapping in behavioral synthesis. 90-95 - Mark Genoe, Paul Vanoostende, Geert van Wauwe:
On the use of VHDL-based behavioral synthesis for telecom ASIC design. 96-103 - Enric Musoll, Jordi Cortadella:
Scheduling and resource binding for low power. 104-109 - Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita:
Power analysis and low-power scheduling techniques for embedded DSP software. 110-115 - Jörg Henkel, Rolf Ernst:
A path-based technique for estimating hardware runtime in HW/SW-cosynthesis. 116-121 - Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu:
A comprehensive estimation technique for high-level synthesis. 122-127 - Matthew F. Parkinson, Sri Parameswaran:
Profiling in the ASP codesign environment. 128-133 - Paul-Gerhard Plöger, Jörg Wilberg, Michel Langevin, Raul Camposano:
WWW based structuring of codesigns. 138-143 - Hans Samsom, Frank H. M. Franssen, Francky Catthoor, Hugo De Man:
System level verification of video and image processing specifications. 144-149 - Jean-Marc Daveau, Tarek Ben Ismail, Ahmed Amine Jerraya:
Synthesis of system-level communication by an allocation-based approach. 150-155 - Jürgen Teich, Lothar Thiele, Edward A. Lee:
Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model. 156-161 - Markus Schwiegershausen, Peter Pirsch:
A system level design methodology for the optimization of heterogeneous multiprocessors. 162-169 - Preeti Ranjan Panda, Nikil D. Dutt:
1995 high level synthesis design repository. 170-174
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