default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID9th MCSoC 2015: Torino/Turin, Italy
- IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2015, Turin, Italy, September 23-25, 2015. IEEE Computer Society 2015, ISBN 978-1-4799-8670-5
- Nicola Bombieri, Federico Busato, Franco Fummi:
An Enhanced Profiling Framework for the Analysis and Development of Parallel Primitives for GPUs. 1-8 - XuanKhanh Do, Stéphane Louise, Albert Cohen:
Managing the Latency of Data-Dependent Tasks in Embedded Streaming Applications. 9-16 - David Defour:
Measuring Predictability of Nvidia's GPU Schedulers: Application to the Summation Problem. 17-24 - Hao Liang
, Yi-Chung Chen, Tao Luo, Wei Zhang, Hai Li, Bingsheng He:
Hierarchical Library Based Power Estimator for Versatile FPGAs. 25-32 - Lei Wang, Yuxing Tang, Yu Deng, Fangyan Qin, Qiang Dou, Guangda Zhang, Feipeng Zhang:
A Scalable and Fast Microprocessor Design Space Exploration Methodology. 33-40 - Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. 41-48 - Ryohei Kobayashi, Kenji Kise:
FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core Systems. 49-56 - Kristoffer Robin Stokke, Håkon Kvale Stensland, Pål Halvorsen, Carsten Griwodz:
Why Race-to-Finish is Energy-Inefficient for Continuous Multimedia Workloads. 57-64 - Eri Ogawa, Yuki Matsuda, Tomohiro Misono, Ryohei Kobayashi, Kenji Kise:
Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and Research. 65-72 - Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima:
A CGRA-Based Approach for Accelerating Convolutional Neural Networks. 73-80 - Alexandre Aminot, Yves Lhuillier, Andrea Castagnetti, Henri-Pierre Charles:
FPU Speedup Estimation for Task Placement Optimization on Asymmetric Multicore Designs. 81-87 - Federico Busato, Nicola Bombieri:
On the Load Balancing Techniques for GPU Applications Based on Prefix-Scan. 88-95 - Oliver Jakob Arndt, Tile Lefherz, Holger Blume:
Abstracting Parallel Programming and Its Analysis Towards Framework Independent Development. 96-103 - Asieh Salehi Fathabadi, Luis Alfonso Maeda-Nunez, Michael J. Butler, Bashir M. Al-Hashimi, Geoff V. Merrett:
Towards Automatic Code Generation of Run-Time Power Management for Embedded Systems Using Formal Methods. 104-111 - Olfa Bali, Walid Elloumi, Pavel Krömer, Adel M. Alimi:
GPU Particle Swarm Optimization Applied to Travelling Salesman Problem. 112-119 - Daniele Bortolotti, Andrea Bartolini, Mauro Mangia, Riccardo Rovatti, Gianluca Setti, Luca Benini:
Energy-Aware Bio-signal Compressed Sensing Reconstruction: FOCUSS on the WBSN-Gateway. 120-126 - Gianvito Urgese, Francesco Barchi, Enrico Macii:
Top-Down Profiling of Application Specific Many-core Neuromorphic Platforms. 127-134 - Anil Kanduri, Amir-Mohammad Rahmani, Pasi Liljeberg, Hannu Tenhunen:
Predictable Application Mapping for Manycore Real-Time and Cyber-Physical Systems. 135-142 - Gasser Ayad, Ramakrishna Nittala, Romain Lemaire:
Automatic Runtime Customization for Variability Awareness on Multicore Platforms. 143-150 - Masoud Oveis Gharan, Gul N. Khan:
Dynamic VC Organization for Efficient NoC Communication. 151-158 - Nicolas Benoit, Stéphane Louise:
A Performance Prediction for Automatic Placement of Heterogeneous Workloads on Many-cores. 159-166 - Amr Saleh Elhelw, Ali El-Moursy, Hossam Ali Hassan Fahmy:
Adaptive Time-Based Least Memory Intensive Scheduling. 167-174 - Gregor Sievers, Julian Daberkow, Johannes Ax, Martin Flasskamp, Wayne Kelly, Thorsten Jungeblut, Mario Porrmann, Ulrich Rückert:
Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI. 175-181 - Ashkan Sadeghi, Kaamran Raahemifar, Mahmood Fathy, Arghavan Asad:
Lighting the Dark-Silicon 3D Chip Multi-processors by Exploiting Heterogeneity in Cache Hierarchy. 182-186 - Chuan Tang, Dan Liu, Zuocheng Xing, Peng Yang, Zhe Wang, Jiang Xu:
Memory Access Analysis of Many-core System with Abundant Bandwidth. 187-194 - Cedric Nugteren, Valeriu Codreanu:
CLTune: A Generic Auto-Tuner for OpenCL Kernels. 195-202 - Riku Murata, Jun Irie, Akihiro Fujii, Teruo Tanaka, Takahiro Katagiri:
Enhancement of Incremental Performance Parameter Estimation on ppOpen-AT. 203-210 - James Price, Simon McIntosh-Smith:
Improving Auto-Tuning Convergence Times with Dynamically Generated Predictive Performance Models. 211-218 - H. Martin Bücker, Ralf Seidler, David Neuhäuser, Tobias Beier:
The Approximate Discrete Radon Transform: A Case Study in Auto-Tuning of OpenCL Implementations. 219-226 - Michael Conrad Meyer, Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah:
FTTDOR: Microring Fault-resilient Optical Router for Reliable Optical Network-on-Chip Systems. 227-234 - Achraf Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah:
Contention-Free Routing for Hybrid Photonic Mesh-Based Network-on-Chip Systems. 235-242 - Johanna Sepúlveda, Sébastien Le Beux, Jiating Luo, Cédric Killian, Daniel Chillet, Hui Li, Ian O'Connor, Olivier Sentieys:
Communication Aware Design Method for Optical Network-on-Chip. 243-250 - Michael Opoku Agyeman, Ji-Xiang Wan, Quoc-Tuan Vien, Wen Zong, Alex Yakovlev, Kenneth Tong, Terrence S. T. Mak:
On the Design of Reliable Hybrid Wired-Wireless Network-on-Chip Architectures. 251-258 - Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano:
3D Shared Bus Architecture Using Inductive Coupling Interconnect. 259-266 - Usman Ali Gulzari, Sheraz Anjum, Shahrukh Agha:
Cross by Pass-Mesh Architecture for On-chip Communication. 267-274 - John R. Feehrer, Jeffry Hughes, Hugh Kurth, David Pabisz, Peter Yakutis:
Implementation and Modeling for High-performance I/O Hub Used in SPARC M7 Processor-Based Servers. 275-282 - Elmira Karimi, Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Mahmoud Tabandeh, Pasi Liljeberg, Zainalabedin Navabi:
Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model. 283-288 - Giuseppe Tagliavini, Germain Haugou, Andrea Marongiu, Luca Benini:
ADRENALINE: An OpenVX Environment to Optimize Embedded Vision Applications on Many-core Accelerators. 289-296 - Alessandro Capotondi, Andrea Marongiu, Luca Benini:
Enabling Scalable and Fine-Grained Nested Parallelism on Embedded Many-cores. 297-304 - Yuichi Sakurai, Ken-ichi Shimbo, Tadanobu Toba, Hideki Osaka:
The Network Performance Analysis Platform and Its Application to Network Buffer Evaluation of the Embedded System. 305-312
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-08 09:49 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
