default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDMLCAD 2025: Santa Cruz, CA, USA
- 7th ACM/IEEE Symposium on Machine Learning for CAD, MLCAD 2025, Santa Cruz, CA, USA, September 8-10, 2025. IEEE 2025, ISBN 979-8-3315-3762-3
- Handong Cho, Taewhan Kim:
Machine-Learning Driven Cell Library Compaction. 1-7 - Minseung Shin, Shilong Zhang, Geuna Chang, Youngsoo Shin:
On-Chip Decoupling Capacitor Placement with Impedance Constraint for DRAM Design. 1-7 - Qijing Wang, Wing Ho Lau, Tsung-Yi Ho, Evangeline F. Y. Young, Martin D. F. Wong:
Dr. Guide: AI-Guided Detailed Routing. 1-7 - Jooyeon Jeong, Taewhan Kim:
Machine Learning Driven Early Clustering for Multi-bit Flip-Flop Allocation. 1-7 - Mohammadamin Hajikhodaverdian, Sherief Reda, Ayse K. Coskun:
Fast Chip Transient Temperature Simulation via Machine Learning. 1-8 - Yanxing Guo, Ling Liang, Zihao Zheng, Zezhi Cheng, Yuhang Yang, Linbo Shan, Zongwei Wang, Yimao Cai:
PROMPT: Prediction Model for RRAM Programming Optimized by Adaptive Mechanism and Progressive Continuous Transformation. 1-7 - Kevin Immanuel Gubbi, Marcus Halm, Sarbani Kumar, Arvind Sudarshan, Pavan Dheeraj Kota, Mohammadnavid Tarighat, Avesta Sasan, Houman Homayoun:
Prompting for Power: Benchmarking Large Language Models for Low-Power RTL Design Generation. 1-7 - Weihua Xiao, Derek Ekberg, Siddharth Garg, Ramesh Karri:
Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVA. 1-10 - Arash Ardakani, Kevin He, John Wawrzynek:
Recurrent CircuitSAT Sampling for Sequential Circuits. 1-7 - Vikram Gopalakrishnan, Atmadip Dey, Rongjian Liang, Yanqing Zhang, Haoxing Ren, Vidya A. Chhabria:
Invited Paper: MLCAD 2025 Contest on ReSynthAI: Physical-aware Logic Resynthesis using AI. 1-7 - Cheng-Hsiang Chiu, Chedi Morchdi, Chih-Chun Chang, Cunxi Yu, Yi Zhou, Tsung-Wei Huang:
Optimizing CUDA Graph Scheduling with Reinforcement Learning - A Case Study in SSTA Propagation. 1-8 - Hang Yang, Yusheng Hu, Yong Liu, Cong Hao:
Pieceformer: Similarity-Driven Knowledge Transfer via Scalable Graph Transformer in VLSI. 1-7 - Hyunmin Jo, Heechun Park:
Priority-Aware Routing Optimization with Full-Path Delay Prediction Using Machine Learning. 1-7 - Zelin Lu, Akhilesh Kumar, Norman Chang, Haiyang He, Lang Lin, Wenbo Xia, Jie Yang, Gang Qu:
Multimodal Learning-Based Thermal Solver for 3DICs with Arbitrary Chip Dimensions and Power Distributions. 1-7 - Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia:
LASSO: LLM-Aided Security Property Generation for Assertion-based SoC Verification. 1-10 - Zahin Ibnat, Paul E. Calzada, Dipayan Saha, Hasan Al Shaikh, Sujan Kumar Saha, Jingbo Zhou, Farimah Farahmandi, Mark Tehranipoor:
Trusting the Machine: How Secure is LLM-Generated RTL Code? 1-8 - Md Rubel Ahmed, Sadiba Nusrat Nur, Rickard Ewetz:
Context-Enhanced Architectural Specification Generation for SoC Designs. 1-7 - Niansong Zhang, Chenhui Deng, Johannes Maximilian Kühn, Chia-Tung Ho, Cunxi Yu, Zhiru Zhang, Haoxing Ren:
ASPEN: LLM-Guided E-Graph Rewriting for RTL Datapath Optimization. 1-9 - Phuoc Pham, Arun Venkitaraman, Chia-Yu Hsieh, Andrea Bonetti, Stefan Uhlich, Markus Leibl, Simon Hofmann, Eisaku Ohbuchi, Lorenzo Servadei, Ulf Schlichtmann, Robert Wille:
GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification. 1-21 - Doyeon Won, Taewhan Kim:
EDA Tool Parameter Optimization Through Fast and Reliable Machine-Learning based Rank Prediction Model. 1-7 - Suresh Purini, Siddhant Garg, Mudit Gaur, Sankalp Bhat, Sohan Mupparapu, Arun Ravindran:
ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis. 1-10 - Chenhui Deng, Yun-Da Tsai, Guan-Ting Liu, Zhongzhi Yu, Haoxing Ren:
ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation. 1-9 - Tianchi Liu, Sriram Madhavan, Dastagiri Dudekula, Luke Thomas, Ivo van Zandvoort, Maarten Berkens:
Industry Track: MAMBO: ML Accelerated Multi-Agent Black-Box Optimization for Enhancing Standard Cell Synthesis Quality. 1-7 - Ziyu Deng, Rada Chirkova, Leigh Anne Clevenger, W. Rhett Davis:
Privacy-Preserving Data and Model Sharing for EDA via Inference Control and DP-SGD. 1-7 - Cunxi Yu:
Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper. 1-7 - Charles Hong, Brendan Roberts, Huijae An, Alex Um, Advay Ratan, Yakun Sophia Shao:
hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation. 1-8 - Yan Tan, Xiangchen Meng, Yangdi Lyu:
LLM-assisted Path Exploration for RTL Verification. 1-7 - Kiran Thorat, Jiahui Zhao, Yaotian Liu, Amit Hasan, Hongwu Peng, Xi Xie, Bin Lei, Caiwen Ding:
LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models. 1-7 - Wei Zeng, Sudipto Kundu, Jerry Wu:
Industry Track: Trajectory.AI: An Automated P&R Flow Trajectory Agent. 1-6 - Yukio Miyasaka, Walter Lau Neto, Eleonora Testa, Anika Prasad, Michael Shuster, Reto Zimmermann, Patrick Vuillod, Alan Mishchenko, John Wawrzynek, Luca G. Amarù:
ML-Inspired Logic Synthesis: Improving Multiplier Circuits. 1-7 - Chun-Yen Huang, Hsuan-I Chen, Hao-Wen Ho, Pei-Hsin Kang, Mark Po-Hung Lin, Wen-Hao Liu, Haoxing Ren:
Netlistify: Transforming Circuit Schematics into Netlists with Deep Learning. 1-8 - Weimin Fu, Yiting Wang, Zelin Lu, Xiaolong Guo, Gang Qu:
HADA: Leveraging Multi-Source Data to Train Large Language Models for Hardware Security Assertion Generation. 1-7 - Ryoga Matsuo, Stefan Uhlich, Arun Venkitaraman, Andrea Bonetti, Chia-Yu Hsieh, Ali Momeni, Lukas Mauch, Augusto Capone, Eisaku Ohbuchi, Lorenzo Servadei:
Schemato - An LLM for Netlist-to-Schematic Conversion. 1-7 - Amur Ghose, Andrew B. Kahng, Sayak Kundu, Zhiang Wang:
ORFS-agent: Tool-Using Agents for Chip Design Optimization. 1-13 - Yuntao Lu, Dehua Liang, Siting Liu, Yuhao Ji, Yu Zhang, Xuanqi Chen, Xia Lin, Jinlei Lu, Weihua Sheng, Bei Yu:
A Hybrid Optimization Framework for Power-Efficient Pulsed Latch Utilization in Clock Networks. 1-7 - Zeng Wang, Minghao Shao, Rupesh Raj Karn, Likhitha Mankali, Jitendra Bhandari, Ramesh Karri, Ozgur Sinanoglu, Muhammad Shafique, Johann Knechtel:
SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design. 1-10 - Jaeheon Jung, Dongwoo Lew, Jangseok Yu, Jongsun Park:
HR2: A PVT Aware Hierarchical RL Based Sizing Framework for Robust Analog Circuit Design. 1-7 - Geuna Chang, Shilong Zhang, Seohyun Kim, Woojin Kim, Youngsoo Shin:
Verilog Code Generation of Hierarchical Design Using LLMs. 1-7 - Minh Luu, Surya Jasper, Khoi Le, Evan Pan, Michael Quinn, Aakash Tyagi, Jiang Hu:
VCDiag: Classifying Erroneous Waveforms for Failure Triage Acceleration. 1-8 - Ming-Yen Lee, Shimeng Yu:
NeuroSim Agent: Automated Compute-In-Memory Accelerator Deployment with Transferable Reinforcement Learning and Dynamic Design Space Pruning. 1-7 - Ishraq Tashdid, Valentina Terry, Jordan Merkel, Tasnuva Farheen, Sazadur Rahman:
BeyondPPA: Human-Inspired Reinforcement Learning for Post-Route Reliability-Aware Macro Placement. 1-12 - Chengjia Liu, Jnana Preeti Parlapalli, David Kebo Houngninou, Michael Quinn, Aakash Tyagi, Jiang Hu:
Improving Last-Mile Coverage in Functional Verification. 1-7 - Surya Selvam, Jacob R. Stevens, Sujit Dey, Anand Raghunathan:
ML-Enhanced Performance and Power Estimation for DNNs on Heterogenous SoCs. 1-7 - Jason Ho, James A. Boyle, Linshen Liu, Andreas Gerstlauer:
LASANA: Large-Scale Surrogate Modeling for Analog Neuromorphic Architecture Exploration. 1-8 - Bekzat Skakov, Sanzhar Abduraimov, Olzhas Nurman, Nursultan Kabylkas:
Firefly: Shedding Light on Verification Gaps using LLM-Powered Mutation Testing. 1-10 - Andrew B. Kahng, Yiting Liu, Zhiang Wang:
Recursive Learning-Based Virtual Buffering for Analytical Global Placement. 1-11 - Surya Jasper, Minh Luu, Evan Pan, Aakash Tyagi, Michael Quinn, Jiang Hu, David Kebo Houngninou:
BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis. 1-9 - Dario Garcia-Gasulla, Gokcen Kestor, Emanuele Parisi, Miquel Albert'i-Binimelis, Cristian Gutierrez, Razine Moundir Ghorab, Orlando Montenegro, Bernat Homs, Miquel Moretó:
TuRTLe: A Unified Evaluation of LLMs for RTL Generation. 1-12 - Ting-Hsun Chi, Charles Mackin, Luyao Shi, Prashanth Vijayaraghavan, Hsinyu Tsai, Ehsan Degan:
RTLExplain: A Structured Approach to RTL Code Summarization and Question Answering for Medium-to-Large Designs Using LLMs. 1-7 - Jingjing Guo, Xuejie Ning, Suohang Yang, Jun Yang, Zhikuang Cai:
Post-Routing Path Statistical Delay Estimation Based on SGAT-GRU Prediction Framework. 1-7
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-11-02 20:53 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
