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ORCIDEvangeline F. Y. Young
F. Y. Young – Fung Yu Young – Evan F. Y. Young
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- affiliation: Chinese University of Hong Kong
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2020 – today
- 2024
[j63]Evangeline F. Y. Young
:
Recap of the 42nd Edition of the International Conference on Computer- Aided Design (ICCAD 2023). IEEE Des. Test 41(2): 88-89 (2024)- [j62]Fangzhou Wang, Jinwei Liu, Wing Ho Lau, Haocheng Li, Evangeline F. Y. Young:
FastPass: A Fast Pin Access Analysis Framework for Detailed Routability Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1566-1579 (2024) - [j61]Lixin Liu, Bangqi Fu, Shiju Lin, Jinwei Liu, Evangeline F. Y. Young, Martin D. F. Wong:
Xplace: An Extremely Fast and Extensible Placement Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1872-1885 (2024) - [j60]Lixin Liu, Tianji Liu, Bentian Jiang, Evangeline F. Y. Young:
Parmesan: Efficient Partitioning and Mapping Flow for DNN Training on General Device Topology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(8): 2426-2439 (2024) - [c137]Bangqi Fu, Lixin Liu, Yang Sun, Wing Ho Lau, Martin D. F. Wong, Evangeline F. Y. Young:
CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs. ASPDAC 2024: 65-70 - [c136]Tianji Liu, Lei Chen, Xing Li, Mingxuan Yuan, Evangeline F. Y. Young:
FineMap: A Fine-grained GPU-parallel LUT Mapping Engine. ASPDAC 2024: 392-397 - [c135]Shiju Lin, Guannan Guo, Tsung-Wei Huang, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong:
GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis. DAC 2024: 71:1-71:6 - [c134]Yang Sun, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young:
Massively Parallel AIG Resubstitution. DAC 2024: 157:1-157:6 - [c133]Shiju Lin, Bentian Jiang, Weihua Sheng, Evangeline F. Y. Young:
Size-Optimized Depth-Constrained Large Parallel Prefix Circuits. DAC 2024: 176:1-176:6 - [c132]Qin Luo, Xinshi Zang, Qijing Wang, Fangzhou Wang, Evangeline F. Y. Young, Martin D. F. Wong:
A Routability-Driven Ultrascale FPGA Macro Placer with Complex Design Constraints. FCCM 2024: 1-7 - [c131]Xinshi Zang, Wenhao Lin, Shiju Lin, Jinwei Liu, Evangeline F. Y. Young:
An Open-Source Fast Parallel Routing Approach for Commercial FPGAs. ACM Great Lakes Symposium on VLSI 2024: 164-169 - [c130]Tianji Liu, Qijing Wang, Lixin Liu, Fangzhou Wang, Evangeline F. Y. Young:
On Advanced Methodologies for Microarchitecture Design Space Exploration. ACM Great Lakes Symposium on VLSI 2024: 376-382 - [c129]Qijing Wang, Jinwei Liu, Martin D. F. Wong, Evangeline F. Y. Young:
A Multi-agent Generative Model for Collaborative Global Routing Refinement. ACM Great Lakes Symposium on VLSI 2024: 383-389 - [c128]Xinshi Zang, Qin Luo, Zhongwei Shao, Jifeng Zhang, Evangeline F. Y. Young, Martin D. F. Wong:
Dynamic Multi-FPGA Prototyping Platforms with Simultaneous Networking, Placement and Routing. ACM Great Lakes Symposium on VLSI 2024: 433-439 - [c127]Qijing Wang, Xiaopeng Zhang, Martin D. F. Wong, Evangeline F. Y. Young:
ControLayout: Conditional Diffusion for Style-Controllable and Violation-Fixable Layout Pattern Generation. ACM Great Lakes Symposium on VLSI 2024: 511-515 - [c126]Evangeline F. Y. Young:
Accelerating Physical Design from 1 to N. ISPD 2024: 227 - [i7]Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou:
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. CoRR abs/2403.07257 (2024) - [i6]Fangzhou Wang, Qijing Wang, Lilas Alrahis, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Ozgur Sinanoglu, Tsung-Yi Ho, Evangeline F. Y. Young, Johann Knechtel:
TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans. CoRR abs/2405.05590 (2024) - [i5]Xinshi Zang, Wenhao Lin, Shiju Lin, Jinwei Liu, Evangeline F. Y. Young:
An Open-Source Fast Parallel Routing Approach for Commercial FPGAs. CoRR abs/2407.00009 (2024) - [i4]Johann Knechtel, Mohammad Eslami, Peng Zou, Min Wei, Xingyu Tong, Binggang Qiu, Zhijie Cai, Guohao Chen, Benchao Zhu, Jiawei Li, Jun Yu, Jianli Chen, Chun-Wei Chiu, Min-Feng Hsieh, Chia-Hsiu Ou, Ting-Chi Wang, Bangqi Fu, Qijing Wang, Yang Sun, Qin Luo, Anthony W. H. Lau, Fangzhou Wang, Evangeline F. Y. Young, Shunyang Bi, Guangxin Guo, Haonan Wu, Zhengguang Tang, Hailong You, Cong Li, Ramesh Karri, Ozgur Sinanoglu, Samuel Pagliarini:
Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. IACR Cryptol. ePrint Arch. 2024: 1440 (2024) - 2023
- [j59]Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young:
PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 164-177 (2023) - [j58]Shiju Lin, Jinwei Liu, Evangeline F. Y. Young, Martin D. F. Wong:
GAMER: GPU-Accelerated Maze Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 583-593 (2023) - [j57]Bentian Jiang, Xinshi Zang, Martin D. F. Wong, Evangeline F. Y. Young:
Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 3067-3077 (2023) - [c125]Dan Zheng, Evangeline F. Y. Young:
An Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA Systems. ASP-DAC 2023: 522-528 - [c124]Jinwei Liu, Evangeline F. Y. Young:
EDGE: Efficient DAG-based Global Routing Engine. DAC 2023: 1-6 - [c123]Tianji Liu, Evangeline F. Y. Young:
Rethinking AIG Resynthesis in Parallel. DAC 2023: 1-6 - [c122]Xinshi Zang, Lei Chen, Xing Li, Wilson W. K. Thong, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong:
CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems. ACM Great Lakes Symposium on VLSI 2023: 357-361 - [c121]Xinshi Zang, Evangeline F. Y. Young, Martin D. F. Wong:
SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems. ACM Great Lakes Symposium on VLSI 2023: 593-598 - [c120]Fangzhou Wang, Jinwei Liu, Evangeline F. Y. Young:
FastPass: Fast Pin Access Analysis with Incremental SAT Solving. ISPD 2023: 9-16 - [c119]Evangeline F. Y. Young:
GPU Acceleration in Physical Synthesis. ISPD 2023: 167 - [c118]Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, Evangeline F. Y. Young:
Security Closure of IC Layouts Against Hardware Trojans. ISPD 2023: 229-237 - 2022
- [j56]Haocheng Li, Wing-Kai Chow, Gengjie Chen, Bei Yu, Evangeline F. Y. Young:
Pin-Accessible Legalization for Mixed-Cell-Height Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 143-154 (2022) - [j55]Bentian Jiang, Jingsong Chen, Jinwei Liu, Lixin Liu, Fangzhou Wang, Xiaopeng Zhang, Evangeline F. Y. Young:
CU.POKer: Placing DNNs on WSE With Optimal Kernel Sizing and Efficient Protocol Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1888-1901 (2022) - [j54]Bentian Jiang, Lixin Liu, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young:
Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2671-2684 (2022) - [c117]Shiju Lin, Jinwei Liu, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young:
NovelRewrite: node-level parallel AIG rewriting. DAC 2022: 427-432 - [c116]Jinwei Liu, Xiaopeng Zhang, Shiju Lin, Xinshi Zang, Jingsong Chen, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young:
Partition and place finite element model on wafer-scale engine. DAC 2022: 631-636 - [c115]Qijing Wang, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young:
A2-ILT: GPU accelerated ILT with spatial attention mechanism. DAC 2022: 967-972 - [c114]Lixin Liu, Bangqi Fu, Martin D. F. Wong, Evangeline F. Y. Young:
Xplace: an extremely fast and extensible global placement framework. DAC 2022: 1309-1314 - [c113]Gracieli Posser, Evangeline F. Y. Young, Stephan Held, Yih-Lang Li, David Z. Pan:
Challenges and Approaches in VLSI Routing. ISPD 2022: 185-192 - [c112]Xiaopeng Zhang, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Evangeline F. Y. Young, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao:
RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement. ITC 2022: 100-107 - [e3]Tulika Mitra, Evangeline F. Y. Young, Jinjun Xiong:
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2022, San Diego, California, USA, 30 October 2022 - 3 November 2022. ACM 2022, ISBN 978-1-4503-9217-4 [contents] - [i3]Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, Evangeline F. Y. Young:
Security Closure of IC Layouts Against Hardware Trojans. CoRR abs/2211.07997 (2022) - 2021
- [j53]Haocheng Li, Satwik Patnaik, Mohammed Ashraf, Haoyu Yang, Johann Knechtel, Bei Yu, Ozgur Sinanoglu, Evangeline F. Y. Young:
Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 1995-2008 (2021) - [c111]Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young:
Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment. ASP-DAC 2021: 176-182 - [c110]Haoyu Yang, Shifan Zhang, Kang Liu, Siting Liu, Benjamin Tan, Ramesh Karri, Siddharth Garg, Bei Yu, Evangeline F. Y. Young:
Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method. ASP-DAC 2021: 885-891 - [c109]Xiaopeng Zhang, Haoyu Yang, Evangeline F. Y. Young:
Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation. DAC 2021: 169-174 - [c108]Jinwei Liu, Gengjie Chen, Evangeline F. Y. Young:
REST: Constructing Rectilinear Steiner Minimum Tree via Reinforcement Learning. DAC 2021: 1135-1140 - [c107]Bentian Jiang, Xiaopeng Zhang, Lixin Liu, Evangeline F. Y. Young:
Building up End-to-end Mask Optimization Framework with Self-training. ISPD 2021: 63-70 - 2020
- [j52]Gengjie Chen, Evangeline F. Y. Young:
SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1217-1230 (2020) - [j51]Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young:
Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1245-1257 (2020) - [j50]Gengjie Chen, Chak-Wa Pui, Haocheng Li, Evangeline F. Y. Young:
Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(9): 1902-1915 (2020) - [j49]Haoyu Yang, Shuhe Li, Zihao Deng, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young:
GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2822-2834 (2020) - [j48]Chak-Wa Pui, Evangeline F. Y. Young:
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. ACM Trans. Design Autom. Electr. Syst. 25(2): 21:1-21:23 (2020) - [j47]Kang Liu, Haoyu Yang, Yuzhe Ma, Benjamin Tan, Bei Yu, Evangeline F. Y. Young, Ramesh Karri, Siddharth Garg:
Adversarial Perturbation Attacks on ML-based CAD: A Case Study on CNN-based Lithographic Hotspot Detection. ACM Trans. Design Autom. Electr. Syst. 25(5): 48:1-48:31 (2020) - [c106]Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young:
CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model. DAC 2020: 1-6 - [c105]Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young:
PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning. ICCAD 2020: 17:1-17:8 - [c104]Bentian Jiang, Lixin Liu, Yuzhe Ma, Hang Zhang, Bei Yu, Evangeline F. Y. Young:
Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization. ICCAD 2020: 20:1-20:9 - [c103]Xiaopeng Zhang, James P. Shiely, Evangeline F. Y. Young:
Layout Pattern Generation and Legalization with Generative Learning Models. ICCAD 2020: 32:1-32:9 - [c102]Bentian Jiang, Jingsong Chen, Jinwei Liu, Lixin Liu, Fangzhou Wang, Xiaopeng Zhang, Evangeline F. Y. Young:
CU.POKer: Placing DNNs on Wafer-Scale Al Accelerator with Optimal Kernel Sizing. ICCAD 2020: 142:1-142:9 - [i2]Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu:
Attacking Split Manufacturing from a Deep Learning Perspective. CoRR abs/2007.03989 (2020)
2010 – 2019
- 2019
- [j46]Haoyu Yang, Jing Su, Yi Zou, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young:
Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1175-1187 (2019) - [j45]Jian Kuang, Evangeline F. Y. Young:
Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1731-1743 (2019) - [j44]Ilgweon Kang, Fang Qiao, Dongwon Park, Daniel Kane, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham:
Three-dimensional Floorplan Representations by Using Corner Links and Partial Order. ACM Trans. Design Autom. Electr. Syst. 24(1): 13:1-13:33 (2019) - [c101]Bentian Jiang, Hang Zhang, Jinglei Yang, Evangeline F. Y. Young:
A fast machine learning-based mask printability predictor for OPC acceleration. ASP-DAC 2019: 412-419 - [c100]Gengjie Chen, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang, Evangeline F. Y. Young:
Detailed routing by sparse grid graph and minimum-area-captured path search. ASP-DAC 2019: 754-760 - [c99]Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu:
Attacking Split Manufacturing from a Deep Learning Perspective. DAC 2019: 135 - [c98]Jingsong Chen, Jinwei Liu, Gengjie Chen, Dan Zheng, Evangeline F. Y. Young:
MARCH: MAze Routing Under a Concurrent and Hierarchical Scheme for Buses. DAC 2019: 216 - [c97]Bentian Jiang, Xiaopeng Zhang, Ran Chen, Gengjie Chen, Peishan Tu, Wei Li, Evangeline F. Y. Young, Bei Yu:
FIT: Fill Insertion Considering Timing. DAC 2019: 221 - [c96]Gengjie Chen, Evangeline F. Y. Young:
Dim Sum: Light Clock Tree by Small Diameter Sum. DATE 2019: 174-179 - [c95]Haocheng Li, Gengjie Chen, Bentian Jiang, Jingsong Chen, Evangeline F. Y. Young:
Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction. ICCAD 2019: 1-7 - [c94]Chak-Wa Pui, Evangeline F. Y. Young:
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. ICCAD 2019: 1-8 - [c93]Evangeline F. Y. Young:
Session details: Patterning and Machine Learning. ISPD 2019 - [c92]Chak-Wa Pui, Gang Wu, Freddy Y. C. Mang, Evangeline F. Y. Young:
An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems. SLIP 2019: 1-8 - [i1]Kang Liu, Haoyu Yang, Yuzhe Ma, Benjamin Tan, Bei Yu, Evangeline F. Y. Young, Ramesh Karri, Siddharth Garg:
Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection. CoRR abs/1906.10773 (2019) - 2018
- [j43]Jian Kuang, Junjie Ye, Evangeline F. Y. Young:
STOMA: Simultaneous Template Optimization and Mask Assignment for Directed Self-Assembly Lithography With Multiple Patterning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1251-1264 (2018) - [j42]Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, Bei Yu:
RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2022-2035 (2018) - [j41]Jian Kuang, Evangeline F. Y. Young, Bei Yu:
CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2036-2049 (2018) - [c91]Chak-Wa Pui, Peishan Tu, Haocheng Li, Gengjie Chen, Evangeline F. Y. Young:
A two-step search engine for large scale boolean matching under NP3 equivalence. ASP-DAC 2018: 592-598 - [c90]Haoyu Yang, Shuhe Li, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young:
GAN-OPC: mask optimization with lithography-guided generative adversarial nets. DAC 2018: 131:1-131:6 - [c89]Haocheng Li, Wing-Kai Chow, Gengjie Chen, Evangeline F. Y. Young, Bei Yu:
Routability-driven and fence-aware legalization for mixed-cell-height circuits. DAC 2018: 150:1-150:6 - [c88]Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F. Y. Young, Zhiru Zhang:
Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. FCCM 2018: 129-132 - [c87]Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young:
Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration. ACM Great Lakes Symposium on VLSI 2018: 261-266 - 2017
- [c86]Jian Kuang, Evangeline F. Y. Young:
Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond. DAC 2017: 61:1-61:6 - [c85]Haoyu Yang, Jing Su, Yi Zou, Bei Yu, Evangeline F. Y. Young:
Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning. DAC 2017: 62:1-62:6 - [c84]Gengjie Chen, Jian Kuang, Zhiliang Zeng, Hang Zhang, Evangeline F. Y. Young, Bei Yu:
Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design. DAC 2017: 70:1-70:6 - [c83]Gengjie Chen, Peishan Tu, Evangeline F. Y. Young:
SALT: Provably good routing topology by a novel steiner shallow-light tree algorithm. ICCAD 2017: 569-576 - [c82]Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu:
Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). ICCAD 2017: 929-936 - [c81]Hang Zhang, Fengyuan Zhu, Haocheng Li, Evangeline F. Y. Young, Bei Yu:
Bilinear Lithography Hotspot Detection. ISPD 2017: 7-14 - [c80]Wing-Kai Chow, Jian Kuang, Peishan Tu, Evangeline F. Y. Young:
Fence-aware detailed-routability driven placement. SLIP 2017: 1-7 - [c79]Peishan Tu, Wing-Kai Chow, Evangeline F. Y. Young:
Timing driven routing tree construction. SLIP 2017: 1-8 - [c78]Haoyu Yang, Yajun Lin, Bei Yu, Evangeline F. Y. Young:
Lithography hotspot detection: From shallow to deep learning. SoCC 2017: 233-238 - 2016
- [j40]Jian Kuang, Evangeline F. Y. Young:
Row-structure stencil planning approaches for E-beam lithography with overlapped characters. Integr. 55: 232-245 (2016) - [j39]Wing-Kai Chow, Evangeline F. Y. Young:
Placement: From Wirelength to Detailed Routability. IPSJ Trans. Syst. LSI Des. Methodol. 9: 2-12 (2016) - [j38]Evangeline F. Y. Young, Azadeh Davoodi:
Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology. ACM Trans. Design Autom. Electr. Syst. 21(3): 36:1 (2016) - [j37]Chuangwen Liu, Peishan Tu, Pangbo Wu, Haomo Tang, Yande Jiang, Jian Kuang, Evangeline F. Y. Young:
An Effective Chemical Mechanical Polishing Fill Insertion Approach. ACM Trans. Design Autom. Electr. Syst. 21(3): 54:1-54:21 (2016) - [j36]Xu He, Yao Wang, Yang Guo, Evangeline F. Y. Young:
Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement. ACM Trans. Design Autom. Electr. Syst. 22(1): 10:1-10:26 (2016) - [j35]Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young:
Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1319-1332 (2016) - [c77]Fang Qiao, Ilgweon Kang, Daniel Kane, Fung Yu Young, Chung-Kuan Cheng, Ronald L. Graham:
3D floorplan representations: Corner links and partial order. 3DIC 2016: 1-5 - [c76]Hang Zhang, Haoyu Yang, Bei Yu, Evangeline F. Y. Young:
VLSI layout hotspot detection based on discriminative feature extraction. APCCAS 2016: 542-545 - [c75]Jian Kuang, Junjie Ye, Evangeline F. Y. Young:
Simultaneous template optimization and mask assignment for DSA with multiple patterning. ASP-DAC 2016: 75-82 - [c74]Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young:
Legalization algorithm for multiple-row height standard cell design. DAC 2016: 83:1-83:6 - [c73]Jian Kuang, Evangeline F. Y. Young:
Optimization for Multiple Patterning Lithography with cutting process and beyond. DATE 2016: 43-48 - [c72]Hang Zhang, Bei Yu, Evangeline F. Y. Young:
Enabling online learning in lithography hotspot detection with information-theoretic feature optimization. ICCAD 2016: 47 - [c71]Jian Kuang, Evangeline F. Y. Young, Bei Yu:
Incorporating cut redistribution with mask assignment to enable 1D gridded design. ICCAD 2016: 48 - [c70]Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu:
RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs. ICCAD 2016: 67 - [e2]Evangeline F. Y. Young, Mustafa Ozdal:
Proceedings of the 2016 on International Symposium on Physical Design, ISPD 2016, Santa Rosa, CA, USA, April 3-6, 2016. ACM 2016, ISBN 978-1-4503-4039-7 [contents] - [r4]Evangeline F. Y. Young:
Slicing Floorplan Orientation. Encyclopedia of Algorithms 2016: 2002-2006 - 2015
- [j34]Johann Knechtel, Evangeline F. Y. Young, Jens Lienig:
Planning Massive Interconnects in 3-D Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1808-1821 (2015) - [c69]Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young:
A robust approach for process variation aware mask optimization. DATE 2015: 1591-1594 - [c68]Zhiqing Liu, Chuangwen Liu, Evangeline F. Y. Young:
An effective triple patterning aware grid-based detailed routing approach. DATE 2015: 1641-1646 - [c67]