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ORCIDACM Journal on Emerging Technologies in Computing Systems, Volume 12
Volume 12, Number 1, July 2015
- Jun Pang, Christopher Dwyer, Alvin R. Lebeck:
mNoC: Large Nanophotonic Network-on-Chip Crossbars with Molecular Scale Devices. 1:1-1:25 - Nahid M. Hossain, Masud H. Chowdhury:
Multilayer Graphene Nanoribbon and Carbon Nanotube Based Floating Gate Transistor for Nonvolatile Flash Memory. 2:1-2:17 - Amirali Ghofrani, Miguel Angel Lastras-Montaño, Siddharth Gaba, Melika Payvand, Wei Lu
, Luke Theogarajan, Kwang-Ting Cheng:
A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory. 3:1-3:18 - Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan:
Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage. 4:1-4:27 - Kyu Ho Park, Woomin Hwang, Hyunchul Seok, Chulmin Kim, Dong-Jae Shin, Dong Jin Kim, Min Kyu Maeng, Seong-Min Kim:
MN-MATE: Elastic Resource Management of Manycores and a Hybrid Memory Hierarchy for a Cloud Node. 5:1-5:25 - Jue Wang, Yuan Xie:
A Write-Aware STTRAM-Based Register File Architecture for GPGPU. 6:1-6:12 - Aldo Romani, Matteo Filippi, Michele Dini, Marco Tartagni:
A Sub-μ A Stand-By Current Synchronous Electric Charge Extractor for Piezoelectric Energy Harvesting. 7:1-7:17 - Hrishikesh Jayakumar, Arnab Raha, Woo Suk Lee, Vijay Raghunathan:
QuickRecall: A HW/SW Approach for Computing across Power Cycles in Transiently Powered Computers. 8:1-8:19 - Chia-Hung Chien, Rodney Van Meter, Sy-Yen Kuo:
Fault-Tolerant Operations for Universal Blind Quantum Computation. 9:1-9:26 - Ching-Hwa Cheng:
SCKVdd: A Scalable Clock-Controlled Self-Stabilized Voltage Technique for Low Power CMOS Digital Circuits. 10:1-10:24
Volume 12, Number 2, August 2015
- Aida Todri-Sanial, Sanjukta Bhanja:
Guest Editorial: Special Issue on Advances in Design of Ultra-Low Power Circuits and Systems in Emerging Technologies. 11:1-11:2 - Pierre-Emmanuel Gaillardon, Edith Beigné, Suzanne Lesecq, Giovanni De Micheli:
A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems. 12:1-12:26 - Can Sitik, Emre Salman, Leo Filippini, Sung-Jun Yoon, Baris Taskin:
FinFET-Based Low-Swing Clocking. 13:1-13:20 - Tiansheng Zhang, Jie Meng, Ayse K. Coskun:
Dynamic Cache Pooling in 3D Multicore Processors. 14:1-14:21 - Santosh Khasanvis, K. M. Masum Habib, Mostafizur Rahman, Roger K. Lake, Csaba Andras Moritz:
Low-Power Heterogeneous Graphene Nanoribbon-CMOS Multistate Volatile Memory Circuit. 15:1-15:18 - Wang Kang, Yue Zhang, Zhaohao Wang, Jacques-Olivier Klein, Claude Chappert, Dafine Ravelosona, Gefei Wang, Youguang Zhang, Weisheng Zhao:
Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology. 16:1-16:42 - Mostafa Rahimi Azghadi, Saber Moradi, Daniel Bernhard Fasnacht, Mehmet Sirin Ozdas, Giacomo Indiveri:
Programmable Spike-Timing-Dependent Plasticity Learning Circuits in Neuromorphic VLSI Architectures. 17:1-17:18 - Mariagrazia Graziano, Azzurra Pulimeno, Ruiyu Wang, Xiang Wei, Massimo Ruo Roch, Gianluca Piccinini:
Process Variability and Electrostatic Analysis of Molecular QCA. 18:1-18:23 - Trong Nhan Le, Alain Pegatoquet, Olivier Berder, Olivier Sentieys, Arnaud Carer:
Energy-Neutral Design Framework for Supercapacitor-Based Autonomous Wireless Sensor Networks. 19:1-19:21
Volume 12, Number 3, September 2015
- Yiyu Shi, Takashi Sato:
Introduction to: Special Issue on Cross-Layer System Design. 20:1-20:2 - Vivek K. De, Andrew B. Kahng, Tanay Karnik, Bao Liu, Milad Maleki, Lu Wang:
Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design. 21:1-21:19 - Milan Patnaik, Chidhambaranathan Rajamanikkam, Chirag Garg, Arnab Roy, V. R. Devanathan, Shankar Balachandran, V. Kamakoti:
ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors. 22:1-22:25 - Chenyuan Zhao, Bryant T. Wysocki, Yifang Liu, Clare Thiem, Nathan R. McDonald, Yang Yi:
Spike-Time-Dependent Encoding for Neuromorphic Processors. 23:1-23:21 - Martin Barke, Ulf Schlichtmann:
A Cross-Layer Approach to Measure the Robustness of Integrated Circuits. 24:1-24:22 - Cheng Zhuo, Houle Gan, Wei-Kai Shih, Alaeddin A. Aydiner:
A Cross-Layer Approach for Early-Stage Power Grid Design and Optimization. 25:1-25:20
- Jinho Lee, Kyungsu Kang, Kiyoung Choi:
REDELF: An Energy-Efficient Deadlock-Free Routing for 3D NoCs with Partial Vertical Connections. 26:1-26:22 - Davide Zoni, William Fornaciari:
Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators. 27:1-27:24 - Xianmin Chen, Niraj K. Jha:
gem5-PVT: A Framework for FinFET System Simulation under PVT Variations. 28:1-28:19 - Tayebeh Bahreini, Naser MohammadZadeh:
An MINLP Model for Scheduling and Placement of Quantum Circuits with a Heuristic Solution Approach. 29:1-29:20 - Mostafizur Rahman, Santosh Khasanvis, Csaba Andras Moritz:
Nanowire Volatile RAM as an Alternative to SRAM. 30:1-30:13
Volume 12, Number 4, July 2016
- Hoda Aghaei Khouzani, Yuan Xue, Chengmo Yang:
Fully Exploiting PCM Write Capacity Within Near Zero Cost Through Segment-Based Page Allocation. 31:1-31:26 - Christophe Layer, Laurent Becker, Kotb Jabeur, Sylvain Claireux, Bernard Dieny, Guillaume Prenat, Gregory di Pendina, Stephane Gros, Pierre Paoli, Virgile Javerliac, Fabrice Bernard-Granger, Loïc Decloedt:
Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories. 32:1-32:24 - Chengwen Wu, Guangyan Zhang, Keqin Li:
Rethinking Computer Architectures and Software Systems for Phase-Change Memory. 33:1-33:40 - Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya:
Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability. 34:1-34:29 - Qian Wang, Yongtae Kim, Peng Li:
Neuromorphic Processors with Memristive Synapses: Synaptic Interface and Architectural Exploration. 35:1-35:22 - Kalyan Biswas, Angsuman Sarkar, Chandan Kumar Sarkar:
Impact of Fin Width Scaling on RF/Analog Performance of Junctionless Accumulation-Mode Bulk FinFET. 36:1-36:12 - Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang:
Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints. 37:1-37:15 - Moon Seok Kim, William Cane-Wissing, Xueqing Li, Jack Sampson, Suman Datta, Sumeet Kumar Gupta, Vijaykrishnan Narayanan:
Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells. 38:1-38:23 - Muhammad Ahsan, Rodney Van Meter, Jungsang Kim:
Designing a Million-Qubit Quantum Computer Using a Resource Performance Simulator. 39:1-39:25 - Mona Arabzadeh, Mahboobeh Houshmand, Mehdi Sedighi, Morteza Saheb Zamani:
Quantum-Logic Synthesis of Hermitian Gates. 40:1-40:15 - Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler:
Embedding of Large Boolean Functions for Reversible Logic. 41:1-41:26 - Aoxiang Tang, Xun Gao, Lung-Yen Chen, Niraj K. Jha:
Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes. 42:1-42:21 - Sourindra M. Chaudhuri, Niraj K. Jha:
Ultra-Low-Leakage and High-Performance Logic Circuit Design Using Multiparameter Asymmetric FinFETs. 43:1-43:25 - Anja von Beuningen, Luca Ramini, Davide Bertozzi, Ulf Schlichtmann:
PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer. 44:1-44:28 - Abbas Dehghani, Kamal Jamshidi:
A Novel Approach to Optimize Fault-Tolerant Hybrid Wireless Network-on-Chip Architectures. 45:1-45:37 - Sparsh Mittal:
A Survey of Architectural Techniques for Near-Threshold Computing. 46:1-46:26
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