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ACM Transactions on Reconfigurable Technology and Systems, Volume 18
Volume 18, Number 1, March 2025
FCCM 2024 Journal Track
- Daniel Hutchings, Adam Taylor

, Jeffrey Goeders
:
Toward FPGA Intellectual Property Encryption from Netlist to Bitstream. 1:1-1:27 - Chenfeng Zhao

, Clayton J. Faber, Roger D. Chamberlain
, Xuan Zhang:
HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures. 2:1-2:26 - Mingqian Sun

, Guangwei Xie, Fan Zhang, Wei Guo, Xitian Fan, Tianyang Li, Li Chen, Jiayu Du:
PTME: A Regular Expression Matching Engine Based on Speculation and Enumerative Computation on FPGA. 3:1-3:28 - Sajjad Tamimi, Arthur Bernhardt

, Florian Stock
, Ilia Petrov, Andreas Koch:
DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP. 4:1-4:33 - Hongzheng Chen

, Jiahao Zhang, Yixiao Du
, Shaojie Xiang
, Zichao Yue
, Niansong Zhang
, Yaohui Cai
, Zhiru Zhang
:
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference. 5:1-5:29 - Ahmed F. AbouElhamayed

, Angela Cui, Javier Fernández-Marqués, Nicholas D. Lane, Mohamed S. Abdelfattah
:
PQA: Exploring the Potential of Product Quantization in DNN Hardware Acceleration. 6:1-6:29 - Shervin Vakili

, Mobin Vaziri
, Amirhossein Zarei
, J. M. Pierre Langlois
:
DyRecMul: Fast and Low-Cost Approximate Multiplier for FPGAs using Dynamic Reconfiguration. 7:1-7:22 - Ryota Miyagi

, Ryota Yasudo, Kentaro Sano, Hideki Takase
:
A Scalable Accelerator for Local Score Computation of Structure Learning in Bayesian Networks. 8:1-8:29 - Giovanni Gozzi

, Michele Fiorito
, Serena Curzel
, Claudio Barone
, Vito Giovanni Castellana, Marco Minutoli
, Antonino Tumeo
, Fabrizio Ferrandi
:
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators. 9:1-9:30 - Matthias Nickel

, Diana Göhringer:
A Survey on Architectures, Hardware Acceleration and Challenges for In-Network Computing. 10:1-10:34
Original Articles
- Aggelos Ferikoglou

, Andreas Kosmas Kakolyris
, Dimosthenis Masouros, Dimitrios Soudris
, Sotirios Xydis
:
CollectiveHLS: A Collaborative Approach to High-Level Synthesis Design Optimization. 11:1-11:32 - Nicolai Fiege

, Peter Zipf:
Fantastic Circuits and Where to Find Them - A Holistic ILP Formulation for Model-Based Hardware Design. 12:1-12:36 - Jordan Leggett

, John McGlone
, Süleyman Sirri Demirsoy, Christian Faerber, Vadim Pelyushenko
:
Accelerating In-memory Database Functionality with FPGAs. 13:1-13:23 - Jiajun Wu

, Mo Song, Jingmin Zhao, Yizhao Gao
, Jia Li
, Hayden Kwok-Hay So
:
TATAA: Programmable Mixed-Precision Transformer Acceleration with a Transformable Arithmetic Architecture. 14:1-14:31 - Juan Encinas

, Alfonso Rodríguez, Andrés Otero
:
Leveraging Incremental Machine Learning for Reconfigurable Systems Modeling under Dynamic Workloads. 15:1-15:27
Volume 18, Number 2, June 2025
- Wenjie Zhou

, Haoyan Qi
, David Boland
, Philip H. W. Leong
:
FPGA-based Block Minifloat Training Accelerator for a Time Series Prediction Network. 16:1-16:23 - Yuhan She

, Jierui Liu
, Yanlong Huang
, Ray C. C. Cheung
, Hong Yan
:
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis. 17:1-17:33 - Giovanni Brignone

, Roberto Bosio
, Fabrizio Ottati
, Claudio Sansoè
, Luciano Lavagno
:
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-specific LLVM Passes for Compute-Intensive FPGA Accelerators. 18:1-18:16 - Tianyou Bao

, Pengzhou He
, Daisuke Fujimoto
, Yuichi Hayashi
, Jiafeng Xie
:
CHIRP: Compact and High-Performance FPGA Implementation of Unified Hardware Accelerators for Ring-Binary-LWE-based PQC. 19:1-19:27 - Daichi Tokuda

, Shinya Takamaeda-Yamazaki
:
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination. 20:1-20:26 - Gaurav Singh

, Kia Bazargan
:
Compressing Neural Networks using Learnable 1D Non-Linear Functions. 21:1-21:33
- Mingqian Sun

, Guangwei Xie
, Fan Zhang
, Wei Guo
, Xitian Fan
, Li Chen
, Jiayu Du
:
FPGA-Based Large-Scale Sorting with Optimized Bandwidth Utilization. 22:1-22:27 - Muhammed Kawser Ahmed

, Maximillian Kealoha Panoff
, Joel Mandebi Mbongue
, Sujan Kumar Saha
, Erman Nghonda Tchinda
, Peter Esenju Mbua
, Christophe Bobda
:
Multi-Tenant Cloud FPGA: A Survey on Security, Trust, and Privacy. 23:1-23:44 - Manolis Ploumidis

, Fabien Chaix
, Nikolaos Chrysos
, Marios Assiminakis
, Nikolaos D. Kallimanis
, Nikolaos Kossifidis
, Michael Nikoloudakis
, Nikolaos Dimou
, Michalis Gianioudis
, George Ieronymakis
, Aggelos Ioannou
, George Kalokerinos
, Pantelis Xirouchakis
, Astrinos Damianakis
, Michael Ligerakis
, Theocharis Vavouris
, Manolis Katevenis
, Vassilis Papaefstathiou
, Manolis Marazakis
, Iakovos Mavroidis
:
The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack. 24:1-24:34 - Keisuke Sugiura

, Hiroki Matsutani
:
FPGA-accelerated Correspondence-free Point Cloud Registration with PointNet Features. 25:1-25:41 - Yaswanth Tavva

, Rohan Juneja
, Trevor E. Carlson
, Li-Shiuan Peh
:
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs. 26:1-26:36 - Xiaochen Hao

, Mingzhe Zhang
, Ce Sun
, Zhuofu Tao
, Hongbo Rong
, Yu Zhang
, Lei He
, Eric Petit
, Wenguang Chen
, Yun Liang
:
Productively Generating a High-Performance Linear Algebra Library on FPGAs. 27:1-27:32 - Seyed Mehdi Mohtavipour

, Hadi Shahriar Shahhoseini
:
PRISA: A Potential Region-based Intelligent Search Algorithm for Dataflow Graph Mapping in Spatial CGRAs. 28:1-28:22 - Yongkang Feng

, Liang Yao
, Hongli Zhou
, Minjie Wu
, Shuai Xiang
, Wanting Sun
, Xiumin Xu
, Yingchun Lu
:
High-Throughput TRNG Design with Novelty Adjustable TDC Based on STR. 29:1-29:24 - Cheng Zuo

, Chang Wu
:
Algorithmic-Level Design Partitioning for Latency Minimization in Multi-Chip and Multi-Die Systems. 30:1-30:19
Volume 18, Number 3, September 2025
- Vaughn Betz

:
Editorial: A Message from the New Editor-in-Chief. 31e:1-31e:2 - Zhenman Fang

:
Introduction to the Special Issue on RAW 2024. 31:1-31:2 - Marco Venere

, Beatrice Branchini
, Davide Conficconi
, Donatella Sciuto
, Marco D. Santambrogio
:
Rock the QASBA: Quantum Error Correction Acceleration via the Sparse Blossom Algorithm on FPGAs. 32:1-32:24 - Federico Valentino

, Beatrice Branchini
, Davide Conficconi
, Donatella Sciuto
, Marco D. Santambrogio
:
QUEKUF: An FPGA Union Find Decoder for Quantum Error Correction on the Toric Code. 33:1-33:26
- Francesco Peverelli

, Daniele Paletti
, Davide Conficconi
:
DFlows: A Flow-Based Programming Approach for a Polyglot Design-Space Exploration Framework. 34:1-34:32 - Guowei Zhu

, Liming Deng
, Kaisen Zhang
, Wang Fan
, Boyin Jin
, Wei Cao
, Fengzhe Zhang
, Xuegong Zhou
, Fan Zhang
, Xinsheng Yu
:
DVHetero: A Framework for Designing and Validating Heterogeneous SoC with RISC-V Processor and CGRA. 35:1-35:30 - Moucheng Yang

, Chengyu Zeng
, Kaixiang Zhu
, Lingli Wang
:
RLUT: A Reduced LUT Architecture with Fine-Grained Scalability and Its Automatic Design Flow for Large Frequent Functions. 36:1-36:32 - Shaoqiang Lu

, Tiandong Zhao
, Ting-Jung Lin
, Rumin Zhang
, Chen Wu
, Lei He
:
MCoreOPU: An FPGA-based Multi-Core Overlay Processor for Transformer-based Models. 37:1-37:27 - Jinwei Xu

, Jingfei Jiang
, Lei Gao
, Xifu Qian
, Yong Dou
:
SPDFA: A Novel Dataflow Fusion Sparse Deep Neural Network Accelerator. 38:1-38:23 - Mohamed A. Elgammal

, Amin Mohaghegh
, Soheil Gholami Shahrouz
, Fatemehsadat Mahmoudi
, Fahrican Kosar
, Kimia Talaei
, Joshua Fife
, Daniel Khadivi
, Kevin E. Murray
, Andrew Boutros
, Kenneth B. Kent
, Jeffrey B. Goeders
, Vaughn Betz
:
VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration. 39:1-39:53 - Zimeng Fan

, Min Peng
:
DGMF: A Unified Dynamic Mapping Framework for Graph Neural Networks. 40:1-40:30 - Geert Roks

, Mario Ruiz Noguera
, Nikolaos Alachiotis
:
Accelerated Phylogenetics on the AMD Versal Adaptive SoC. 41:1-41:26 - Mustafa Ibrahim

, Sébastien Pillement
, Andréa Pinna
, Sébastien Le Nours
:
VERSATILE: Very Fast Partial Reconfiguration Controller. 42:1-42:22

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