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ORCIDYun Liang 0001
Person information
- affiliation: Peking University, Center for Energy-Efficient Computing and Applications, Beijing, China
- affiliation (2010 - 2012): University of Illinois Urbana-Champaign, Urbana, IL, USA
- affiliation (PhD 2010): National University of Singapore, Singapore
Other persons with the same name
- Yun Liang 0003
![[0000-0003-0799-0054]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0003-0799-0054")
— South China Agricultural University, Guangzhou, China (and 1 more) - Yun Liang 0004 — China Electric Power Research Institute, Beijing, China (and 1 more)
- Yun Liang 0005 — Guangxi Polytechnic of Construction, Nanning, China
- Yun Liang 0007 — Northwest Regional Climate Center, Lanzhou, China
- Yun Liang 0008 — Indiana University School of Medicine, Indianapolis, IN, USA (and 1 more)
- Yun Liang 0009 — Shanghai Dianji University, China
- Yun Liang 0010 — Duke University, Durham, NC, USA
- Yun Liang 0011 — Institute of Global Energy Internet, State Grid Laboratory of Electric Power Communication Network Technology, Nanjing, China
- Yun Liang 0012 — University of Florida, Department of Biomedical Engineering, Gainesville, FL, USA
- Yun Liang 0013 — Shanxi University, Research Center for Philosophy of Science and Technology, Taiyuan, China
- Yun Liang 0014 — Hokkaido University, Graduate School of Information Science and Technology, Sapporo, Japan
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2020 – today
- 2020
[j26]Qingcheng Xiao, Yun Liang:
Fune: An FPGA Tuning Framework for CNN Acceleration. IEEE Des. Test 37(1): 46-55 (2020)- [j25]Liancheng Jia, Liqiang Lu, Xuechao Wei, Yun Liang:
Generating Systolic Array Accelerators With Reusable Blocks. IEEE Micro 40(4): 85-92 (2020) - [j24]Liancheng Jia, Yun Liang, Xiuhong Li, Liqiang Lu, Shengen Yan:
Enabling Efficient Fast Convolution Algorithms on GPUs via MegaKernels. IEEE Trans. Computers 69(7): 986-997 (2020) - [j23]Yun Liang, Liqiang Lu, Qingcheng Xiao, Shengen Yan:
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 857-870 (2020) - [j22]Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He:
Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1428-1441 (2020) - [j21]Jingchen Zhu, Guangyu Sun, Xian Zhang, Chao Zhang, Weiqi Zhang, Yun Liang, Tao Wang, Yiran Chen, Jia Di:
Fork Path: Batching ORAM Requests to Remove Redundant Memory Accesses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2279-2292 (2020) - [c77]Size Zheng, Yun Liang, Shuo Wang, Renze Chen, Kaiwen Sheng:
FlexTensor: An Automatic Schedule Exploration and Optimization Framework for Tensor Computation on Heterogeneous System. ASPLOS 2020: 859-873 - [c76]Qingcheng Xiao, Liqiang Lu, Jiaming Xie, Yun Liang:
FCNNLib: An Efficient and Flexible Convolution Algorithm Library on FPGAs. DAC 2020: 1-6 - [c75]Tao Yang, Yunkun Liao, Jianping Shi, Yun Liang, Naifeng Jing, Li Jiang:
A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern. FPL 2020: 254-261 - [c74]Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey:
SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. ICCAD 2020: 73:1-73:9 - [i8]Hongbo Rong, Xiaochen Hao, Yun Liang, Lidong Xu, Hong H. Jiang, Pradeep Dubey:
Systolic Computing on GPUs for Productive Performance. CoRR abs/2010.15884 (2020)
2010 – 2019
- 2019
- [c73]Jiaming Xie, Yun Liang:
SPART: Optimizing CNNs by Utilizing Both Sparsity of Weights and Feature Maps. APPT 2019: 71-85 - [c72]Xuechao Wei, Yun Liang, Jason Cong:
Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management. DAC 2019: 125 - [c71]Runbin Shi, Junjie Liu, Hayden Kwok-Hay So, Shuo Wang, Yun Liang:
E-LSTM: Efficient Inference of Sparse LSTM on Embedded Heterogeneous System. DAC 2019: 182 - [c70]Jingjing Xu, Liang Zhao, Hanqi Yan, Qi Zeng, Yun Liang, Xu Sun:
LexicalAT: Lexical-Based Adversarial Reinforcement Training for Robust Sentiment Classification. EMNLP/IJCNLP (1) 2019: 5517-5526 - [c69]Liqiang Lu, Jiaming Xie, Ruirui Huang, Jiansong Zhang, Wei Lin, Yun Liang:
An Efficient Hardware Accelerator for Sparse Convolutional Neural Networks on FPGAs. FCCM 2019: 17-25 - [c68]Caiwen Ding, Shuo Wang, Ning Liu, Kaidi Xu, Yanzhi Wang, Yun Liang:
REQ-YOLO: A Resource-Aware, Efficient Quantization Framework for Object Detection on FPGAs. FPGA 2019: 33-42 - [c67]Xuechao Wei, Yun Liang, Peng Zhang, Cody Hao Yu, Jason Cong:
Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment. FPGA 2019: 120 - [c66]Liqiang Lu, Yun Liang, Ruirui Huang, Wei Lin, Xiaoyuan Cui, Jiansong Zhang:
Speedy: An Accelerator for Sparse Convolutional Neural Networks on FPGAs. FPGA 2019: 187 - [c65]Shuo Wang, Yun Liang, Wei Zhang:
Poly: Efficient Heterogeneous System and Application Management for Interactive Applications. HPCA 2019: 199-210 - [c64]Xiaolong Xie, Yun Liang, Xiuhong Li, Wei Tan:
CuLDA: Solving Large-scale LDA Problems on GPUs. HPDC 2019: 195-205 - [c63]Qingcheng Xiao, Yun Liang:
Zac: Towards Automatic Optimization and Deployment of Quantized Deep Neural Networks on Embedded Devices. ICCAD 2019: 1-6 - [c62]Xu Xia, Lei Zhang, Chengli Mei, Jinyan Li, Xuetian Zhu, Yun Liang, Jeffrey Song:
A Survey on 5G Network Slicing Enabling the Smart Grid. ICPADS 2019: 911-916 - [c61]Jiaxi Zhang, Wentai Zhang, Guojie Luo, Xuechao Wei, Yun Liang, Jason Cong:
Frequency Improvement of Systolic Array-Based CNNs on FPGAs. ISCAS 2019: 1-4 - [c60]Xiuhong Li, Yun Liang, Shengen Yan, Liancheng Jia, Yinghan Li:
A coordinated tiling and batching framework for efficient GEMM on GPUs. PPoPP 2019: 229-241 - [c59]Xiaolong Xie, Yun Liang, Xiuhong Li, Wei Tan:
CuLDA_CGS: solving large-scale LDA problems on GPUs. PPoPP 2019: 435-436 - [i7]Caiwen Ding, Shuo Wang, Ning Liu, Kaidi Xu, Yanzhi Wang, Yun Liang:
REQ-YOLO: A Resource-Aware, Efficient Quantization Framework for Object Detection on FPGAs. CoRR abs/1909.13396 (2019) - 2018
- [j20]Zhenxin Fu, Lei Yang, Wenbin Hou, Zhuohan Li, Yifan Wu, Yihua Cheng, Xiaolin Wang, Yun Liang:
Student Cluster Competition 2017, Team Peking University: Reproducing vectorization of the Tersoff multi-body potential on the Intel Broadwell architecture. Parallel Comput. 78: 28-32 (2018) - [j19]Xiaolong Xie, Yun Liang, Xiuhong Li, Yudong Wu, Guangyu Sun, Tao Wang, Dongrui Fan:
CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs. IEEE Trans. Computers 67(6): 890-897 (2018) - [j18]Yun Liang, Shuo Wang, Wei Zhang:
FlexCL: A Model of Performance and Power for OpenCL Workloads on FPGAs. IEEE Trans. Computers 67(12): 1750-1764 (2018) - [j17]Yun Liang, Xiaolong Xie, Yu Wang, Guangyu Sun, Tao Wang:
Optimizing Cache Bypassing and Warp Scheduling for GPUs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1560-1573 (2018) - [j16]Xinfeng Xie, Dayou Du, Qian Li, Yun Liang, Wai Teng Tang, Zhongliang Ong, Mian Lu, Huynh Phung Huynh, Rick Siow Mong Goh:
Exploiting Sparsity to Accelerate Fully Connected Layers of CNN-Based Applications on Mobile SoCs. ACM Trans. Embed. Comput. Syst. 17(2): 37:1-37:25 (2018) - [c58]Yun Liang, Shuo Wang, Tulika Mitra, Yajun Ha:
Analytical Two-Level Near Threshold Cache Exploration for Low Power Biomedical Applications. ACA 2018: 95-108 - [c57]Liqiang Lu, Yun Liang:
SpWA: an efficient sparse winograd convolutional neural networks accelerator on FPGAs. DAC 2018: 135:1-135:6 - [c56]Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang:
CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms. FCCM 2018: 165-172 - [c55]Shuo Wang, Zhe Li, Caiwen Ding, Bo Yuan, Qinru Qiu, Yanzhi Wang, Yun Liang:
C-LSTM: Enabling Efficient LSTM using Structured Compression Techniques on FPGAs. FPGA 2018: 11-20 - [c54]Xuechao Wei, Yun Liang, Xiuhong Li, Cody Hao Yu, Peng Zhang, Jason Cong:
TGPA: tile-grained pipeline architecture for low latency CNN inference. ICCAD 2018: 58 - [c53]Zhe Li, Shuo Wang, Caiwen Ding, Qinru Qiu, Yanzhi Wang, Yun Liang:
Efficient Recurrent Neural Networks using Structured Matrices in FPGAs. ICLR (Workshop) 2018 - [c52]Xiuhong Li, Yun Liang, Wentai Zhang, Taide Liu, Haochen Li, Guojie Luo, Ming Jiang:
cuMBIR: An Efficient Framework for Low-dose X-ray CT Image Reconstruction on GPUs. ICS 2018: 184-194 - [i6]Xiaolong Xie, Yun Liang, Xiuhong Li, Wei Tan:
CuLDA_CGS: Solving Large-scale LDA Problems on GPUs. CoRR abs/1803.04631 (2018) - [i5]Shuo Wang, Zhe Li, Caiwen Ding, Bo Yuan, Yanzhi Wang, Qinru Qiu, Yun Liang:
C-LSTM: Enabling Efficient LSTM using Structured Compression Techniques on FPGAs. CoRR abs/1803.06305 (2018) - [i4]Zhe Li, Shuo Wang, Caiwen Ding, Qinru Qiu, Yanzhi Wang, Yun Liang:
Efficient Recurrent Neural Networks using Structured Matrices in FPGAs. CoRR abs/1803.07661 (2018) - [i3]Shaokai Ye, Tianyun Zhang, Kaiqi Zhang, Jiayu Li, Jiaming Xie, Yun Liang, Sijia Liu, Xue Lin, Yanzhi Wang:
A Unified Framework of DNN Weight Pruning and Weight Clustering/Quantization Using ADMM. CoRR abs/1811.01907 (2018) - 2017
- [j15]Lei Yang, Yilong Li, Zhenxin Fu, Zhuohan Li, Wenbin Hou, Haoze Wu, Xiaolin Wang, Yun Liang:
ParConnect reproducibility report. Parallel Comput. 70: 22-26 (2017) - [j14]Yun Liang, Wai Teng Tang, Ruizhe Zhao, Mian Lu, Huynh Phung Huynh, Rick Siow Mong Goh:
Scale-Free Sparse Matrix-Vector Multiplication on Many-Core Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12): 2106-2119 (2017) - [j13]Yun Liang, Xiuhong Li:
Efficient Kernel Management on GPUs. ACM Trans. Embed. Comput. Syst. 16(4): 115:1-115:24 (2017) - [c51]Xuechao Wei, Yun Liang, Tao Wang, Songwu Lu, Jason Cong:
Throughput optimization for streaming applications on CPU-FPGA heterogeneous systems. ASP-DAC 2017: 488-493 - [c50]Yun Liang:
Programming FPGAs Using OpenCL from Performance Model to Application Study. ETCD@ASPLOS 2017: 11:1 - [c49]Shuo Wang, Yun Liang, Wei Zhang:
FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs. DAC 2017: 27:1-27:6 - [c48]Shuo Wang, Yun Liang:
A Comprehensive Framework for Synthesizing Stencil Algorithms on FPGAs using OpenCL Model. DAC 2017: 28:1-28:6 - [c47]Xuechao Wei, Cody Hao Yu, Peng Zhang, Youxiang Chen, Yuxin Wang, Han Hu, Yun Liang, Jason Cong:
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs. DAC 2017: 29:1-29:6 - [c46]Qingcheng Xiao, Yun Liang, Liqiang Lu, Shengen Yan, Yu-Wing Tai:
Exploring Heterogeneous Algorithms for Accelerating Deep Convolutional Neural Networks on FPGAs. DAC 2017: 62:1-62:6 - [c45]Guanwen Zhong, Alok Prakash, Siqi Wang, Yun Liang, Tulika Mitra, Smaïl Niar:
Design Space exploration of FPGA-based accelerators with multi-level parallelism. DATE 2017: 1141-1146 - [c44]Liqiang Lu, Yun Liang, Qingcheng Xiao, Shengen Yan:
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs. FCCM 2017: 101-108 - [c43]Shuo Wang, Yun Liang:
A Framework for Iterative Stencil Algorithm Synthesis on FPGAs from OpenCL Programming Model (Abstract Only). FPGA 2017: 285-286 - [c42]Xiaolong Xie, Wei Tan, Liana L. Fong, Yun Liang:
CuMF_SGD: Parallelized Stochastic Gradient Descent for Matrix Factorization on GPUs. HPDC 2017: 79-92 - [c41]Yun Liang, Xiuhong Li, Xiaolong Xie:
Exploring cache bypassing and partitioning for multi-tasking on GPUs. ICCAD 2017: 9-16 - [c40]Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He:
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications. ICCAD 2017: 430-437 - [c39]Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang:
A hybrid approach to cache management in heterogeneous CPU-FPGA platforms. ICCAD 2017: 937-944 - [c38]Qian Li, Qingcheng Xiao, Yun Liang:
Enabling high performance deep learning networks on embedded systems. IECON 2017: 8405-8410 - 2016
- [j12]Yun Liang, Shuo Wang:
Performance-Centric Optimization for Racetrack Memory Based Register File on GPUs. J. Comput. Sci. Technol. 31(1): 36-49 (2016) - [j11]Yun Liang, Muhammad Teguh Satria, Kyle Rupnow, Deming Chen:
An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7): 1165-1178 (2016) - [j10]Ying Chen, Tan Nguyen, Yao Chen, Swathi T. Gurumani, Yun Liang, Kyle Rupnow, Jason Cong, Wen-mei W. Hwu, Deming Chen:
FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2032-2045 (2016) - [j9]Yao Chen, Swathi T. Gurumani, Yun Liang, Guofeng Li, Donghui Guo, Kyle Rupnow, Deming Chen:
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2220-2233 (2016) - [c37]Shuo Wang, Yun Liang, Chao Zhang, Xiaolong Xie, Guangyu Sun, Yongpan Liu, Yu Wang, Xiuhong Li:
Performance-centric register file design for GPUs using racetrack memory. ASP-DAC 2016: 25-30 - [c36]Guanwen Zhong, Alok Prakash, Yun Liang, Tulika Mitra, Smaïl Niar:
Lin-analyzer: a high-level performance analysis tool for FPGA-based accelerators. DAC 2016: 136:1-136:6 - [c35]Xiuhong Li, Yun Liang:
Efficient kernel management on GPUs. DATE 2016: 85-90 - [i2]Xiaolong Xie, Wei Tan, Liana L. Fong, Yun Liang:
CuMF_SGD: Fast and Scalable Matrix Factorization. CoRR abs/1610.05838 (2016) - 2015
- [j8]Yun Liang, Tulika Mitra, Lei Ju:
Instruction Cache Locking Using Temporal Reuse Profile. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(9): 1387-1400 (2015) - [j7]Yun Liang, Xiaolong Xie, Guangyu Sun, Deming Chen:
An Efficient Compiler Framework for Cache Bypassing on GPUs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(10): 1677-1690 (2015) - [j6]Yun Liang, Huynh Phung Huynh, Kyle Rupnow, Rick Siow Mong Goh, Deming Chen:
Efficient GPU Spatial-Temporal Multitasking. IEEE Trans. Parallel Distributed Syst. 26(3): 748-760 (2015) - [j5]Mian Lu, Yun Liang, Huynh Phung Huynh, Zhongliang Ong, Bingsheng He, Rick Siow Mong Goh:
MrPhi: An Optimized MapReduce Framework on Intel Xeon Phi Coprocessors. IEEE Trans. Parallel Distributed Syst. 26(11): 3066-3078 (2015) - [c34]Yun Liang, Shuo Wang:
Quantitative performance and power analysis of LTE using high level synthesis. ASICON 2015: 1-4 - [c33]Wai Teng Tang, Ruizhe Zhao, Mian Lu, Yun Liang, Huynh Phung Huyng, Xibai Li, Rick Siow Mong Goh:
Optimizing and auto-tuning scale-free sparse matrix-vector multiplication on Intel Xeon Phi. CGO 2015: 136-145 - [c32]Xiaolong Xie, Yun Liang, Yu Wang, Guangyu Sun, Tao Wang:
Coordinated static and dynamic cache bypassing for GPUs. HPCA 2015: 76-88 - [c31]Chao Zhang, Guangyu Sun, Xian Zhang, Weiqi Zhang, Weisheng Zhao, Tao Wang, Yun Liang, Yongpan Liu, Yu Wang, Jiwu Shu:
Hi-fi playback: tolerating position errors in shift operations of racetrack memory. ISCA 2015: 694-706 - [c30]Xian Zhang, Guangyu Sun, Chao Zhang, Weiqi Zhang, Yun Liang, Tao Wang, Yiran Chen, Jia Di:
Fork path: improving efficiency of ORAM by removing redundant memory accesses. MICRO 2015: 102-114 - [c29]Xiaolong Xie, Yun Liang, Xiuhong Li, Yudong Wu, Guangyu Sun, Tao Wang, Dongrui Fan:
Enabling coordinated register allocation and thread-level parallelism optimization for GPUs. MICRO 2015: 395-406 - 2014
- [c28]Xiaoming Chen, Yu Wang, Yun Liang, Yuan Xie, Huazhong Yang:
Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs. DAC 2014: 168:1-168:6 - [c27]Huping Ding, Yun Liang, Tulika Mitra:
WCET-Centric dynamic instruction cache locking. DATE 2014: 1-6 - [c26]Swathi T. Gurumani, Jacob Tolar, Yao Chen, Yun Liang, Kyle Rupnow, Deming Chen:
Integrated CUDA-to-FPGA Synthesis with Network-on-Chip. FCCM 2014: 21-24 - [c25]Guanwen Zhong, Vanchinathan Venkataramani, Yun Liang, Tulika Mitra, Smaïl Niar:
Design space exploration of multiple loops on FPGAs using high level synthesis. ICCD 2014: 456-463 - [c24]Zhimin Wu, Yang Liu, Yun Liang, Jun Sun:
GPU Accelerated Counterexample Generation in LTL Model Checking. ICFEM 2014: 413-429 - [c23]Jingyu Deng, Yun Liang, Guojie Luo, Guangyu Sun:
Rapid design space exploration of two-level unified caches. ISCAS 2014: 1937-1940 - 2013
- [j4]Yun Liang, Tulika Mitra:
An analytical approach for fast and accurate design space exploration of instruction caches. ACM Trans. Embed. Comput. Syst. 13(3): 43:1-43:29 (2013) - [c22]Swathi T. Gurumani, Hisham Cholakkal, Yun Liang, Kyle Rupnow, Deming Chen:
High-level synthesis of multiple dependent CUDA kernels on FPGA. ASP-DAC 2013: 305-312 - [c21]Yun Liang, Zheng Cui, Kyle Rupnow, Deming Chen:
Register and thread structure optimization for GPUs. ASP-DAC 2013: 461-466 - [c20]Huping Ding, Yun Liang, Tulika Mitra:
Shared cache aware task mapping for WCRT minimization. ASP-DAC 2013: 735-740 - [c19]Mian Lu, Lei Zhang, Huynh Phung Huynh, Zhongliang Ong, Yun Liang, Bingsheng He, Rick Siow Mong Goh, Richard Huynh:
Optimizing the MapReduce framework on Intel Xeon Phi coprocessor. BigData 2013: 125-130 - [c18]Alexandros Papakonstantinou, Deming Chen, Wen-mei W. Hwu, Jason Cong, Yun Liang:
Throughput-oriented kernel porting onto FPGAs. DAC 2013: 11:1-11:10 - [c17]Huping Ding, Yun Liang, Tulika Mitra:
Integrated instruction cache analysis and locking in multitasking real-time systems. DAC 2013: 147:1-147:10 - [c16]Wei Zuo, Yun Liang, Peng Li, Kyle Rupnow, Deming Chen, Jason Cong:
Improving high level synthesis optimization opportunity through polyhedral transformations. FPGA 2013: 9-18 - [c15]Xiaolong Xie, Yun Liang, Guangyu Sun, Deming Chen:
An efficient compiler framework for cache bypassing on GPUs. ICCAD 2013: 516-523 - [i1]Mian Lu, Lei Zhang, Huynh Phung Huynh, Zhongliang Ong, Yun Liang, Bingsheng He, Rick Siow Mong Goh, Richard Huynh:
Optimizing the MapReduce Framework on Intel Xeon Phi Coprocessor. CoRR abs/1309.0215 (2013) - 2012
- [j3]Yun Liang, Kyle Rupnow, Yinan Li, Dongbo Min, Minh N. Do, Deming Chen:
High-Level Synthesis: Productivity, Performance, and Software Constraints. J. Electr. Comput. Eng. 2012: 649057:1-649057:14 (2012) - [j2]Yun Liang, Huping Ding, Tulika Mitra, Abhik Roychoudhury, Yan Li, Vivy Suhendra:
Timing analysis of concurrent programs running on shared cache multi-cores. Real Time Syst. 48(6): 638-680 (2012) - [c14]Huping Ding, Yun Liang, Tulika Mitra:
WCET-centric partial instruction cache locking. DAC 2012: 412-420 - [c13]Yun Liang, Zheng Cui, Shengkui Zhao, Kyle Rupnow, Yihao Zhang, Douglas L. Jones, Deming Chen:
Real-time implementation and performance optimization of 3D sound localization on GPUs. DATE 2012: 832-835 - [c12]Zheng Cui, Yun Liang, Kyle Rupnow, Deming Chen:
An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization. IPDPS 2012: 83-94 - 2011
- [c11]Kyle Rupnow, Yun Liang, Yinan Li, Deming Chen:
A study of high-level synthesis: Promises and challenges. ASICON 2011: 1102-1105 - [c10]Alexandros Papakonstantinou, Yun Liang, John A. Stratton, Karthik Gururaj, Deming Chen, Wen-mei W. Hwu, Jason Cong:
Multilevel Granularity Parallelism Synthesis on FPGAs. FCCM 2011: 178-185 - [c9]Kyle Rupnow, Yun Liang, Yinan Li, Dongbo Min, Minh N. Do, Deming Chen:
High level synthesis of stereo matching: Productivity, performance, and software constraints. FPT 2011: 1-8 - 2010
- [c8]Yun Liang, Tulika Mitra:
Improved procedure placement for set associative caches. CASES 2010: 147-156 - [c7]Yun Liang, Tulika Mitra:
Instruction cache locking using temporal reuse profile. DAC 2010: 344-349 - [c6]Huynh Phung Huynh, Yun Liang, Tulika Mitra:
Efficient custom instructions generation for system-level design. FPT 2010: 445-448 - [c5]Bowen Du, Yun Liang, Dianfu Ma, Weifeng Lv, Tongyu Zhu:
An Efficient Algorithm to Estimate Real-time Traffic Information based on Multiple Data Sources. ICAART (1) 2010: 507-510
2000 – 2009
- 2009
- [j1]Lei Ju, Yun Liang, Samarjit Chakraborty, Tulika Mitra, Abhik Roychoudhury:
Cache-aware optimization of BAN applications. Des. Autom. Embed. Syst. 13(3): 159-178 (2009) - [c4]Yan Li, Vivy Suhendra, Yun Liang, Tulika Mitra, Abhik Roychoudhury:
Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores. RTSS 2009: 57-67 - 2008
- [c3]Yun Liang, Tulika Mitra:
Static analysis for fast and accurate design space exploration of caches. CODES+ISSS 2008: 103-108 - [c2]Yun Liang, Lei Ju, Samarjit Chakraborty, Tulika Mitra, Abhik Roychoudhury:
Cache-aware optimization of BAN applications. CODES+ISSS 2008: 149-154 - [c1]Yun Liang, Tulika Mitra:
Cache modeling in probabilistic execution time analysis. DAC 2008: 319-324
Coauthor Index