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ORCIDVLSI Design, Volume 5
Volume 5, Number 1, 1996
- Kuo-En Chang, Sei-Wang Chen:
An Efficient and Fast Algorithm for Routing Over the Cells. 1-10 - Dinesh Bhatia
, V. Shankar:
Greedy Segmented Channel Router. 11-21 - Gudni Gudmundsson, Simeon C. Ntafos:
A Greedy Algorithm for Over-The-Cell Channel Routing. 23-36 - Youssef Saab:
A Fast Clustering-Based Min-Cut Placement Algorithm With Simulated-Annealing Performance. 37-48 - Bhanu Kapoor, V. S. S. Nair:
Improving Path Sensitizability of Combinational Circuits. 49-57 - Jiabi Zhu, Mostafa I. H. Abd-El-Barr, Carl McCrosky:
A New Theory for Testability-Preserving Optimization of Combinational Circuits. 59-75 - C. P. Ravikumar, Vikram Saxena:
TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis. 77-87 - Donald T. Comer:
Zener Zap Anti-Fuse Trim in VLSI Circuits. 89-100 - Murray W. Pearson, Paul J. Lyons, Mark D. Apperley:
High-Level Graphical Abstraction in Digital Design. 101-110
Volume 5, Number 2, 1997
- Fadi J. Kurdahi:
Linking Behavioral, Structural, and Physical Models of Hardware. i-ii - Massoud Pedram, Narasimha B. Bhat, Ernest S. Kuh:
Combining Technology Mapping With Layout. 111-124 - Mandalagiri S. Chandrasekhar, Robert H. McCharles, David E. Wallace:
Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits. 125-140 - Akhilesh Tyagi:
Statistical Module Level Area and Delay Estimation. 141-153 - Nikil D. Dutt, Pradip K. Jha:
RT Component Sets for High-Level Design Applications. 155-165 - Ian G. Harris, Alex Orailoglu:
Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction. 167-182 - Jen-Pin Weng, Alice C. Parker:
Taking Thermal Considerations Into Account During High-Level Synthesis. 183-193 - Allen C.-H. Wu:
Datapath Optimization Using Layout Information: An Empirical Study. 195-209 - Fur-Shing Tsai, Yu-Chin Hsu:
Layout Modeling and Design Space Exploration in Pss1 System. 211-221
Volume 5, Number 3, 1997
- Rafic Z. Makki:
Advancements in Power Supply Current Testing. i-ii - Mahmoud Al-Qutayri, Peter R. Shepherd:
Application of Dynamic Supply Current Monitoring to Testing Mixed-Signal Circuits. 223-240 - Eugeni Isern, Joan Figueras:
IDDQ Detectable Bridges in Combinational CMOS Circuits. 241-252 - Abdulnour Y. Toukmaji, Ronald Helms, Rafic Z. Makki, Wadie Mikhail, Patrick Toole:
IDDQ Testing Experiments for Various CMOS Logic Design Structures. 253-271 - Víctor H. Champac, Joan Figueras:
Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects. 273-284 - Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana, Carol Q. Tong:
Operational and Test Performance in the Presence of Built-in Current Sensors. 285-298 - Suntae Hwang, Rochit Rajsuman:
VLSI Testing for High Reliability: Mixing IDDQ Testing With Logic Testing. 299-311
Volume 5, Number 4, 1998
- Parag K. Lala:
Guest Editorial. - Mark G. Karpovsky:
Integrated On-Line and Off-Line Error Detection Mechanisms in the Coding Theory Framework. 313-331 - Andrej A. Morosov, Valerij V. Saposhnikov, Vladimir V. Saposhnikov, Michael Gössel:
Self-Checking Combinational Circuits with Unidirectionally Independent Outputs. 333-345 - Steffen Tarnick:
Embedded Parity and Two-Rail TSC Checkers with Error-Memorizing Capability. 347-356 - Yeong-Ruey Shieh, Cheng-Wen Wu:
Design of CMOS PSCD Circuits and Checkers for Stuck-At and Stuck-On Faults. 357-372 - Jien-Chung Lo:
A Case Study of Self-Checking Circuits Reliability. 373-383 - Feodor S. Vainstein:
Self Checking Design Technique for Numerical Computations. 385-392
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