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F. Joel Ferguson
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Publications
- 1998
- [j10]David B. Lavo, Brian Chess, Tracy Larrabee, F. Joel Ferguson:
Diagnosing realistic bridging faults with single stuck-at information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(3): 255-268 (1998) - [j9]Haluk Konuk, F. Joel Ferguson:
Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(11): 1200-1210 (1998) - [c24]Jayashree Saxena, Kenneth M. Butler, Hari Balachandran, David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess:
On applying non-classical defect models to automated diagnosis. ITC 1998: 748-757 - [c22]Douglas Williams, F. Joel Ferguson, Tracy Larrabee:
A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric. VTS 1998: 274-282 - 1997
- [c21]Haluk Konuk, F. Joel Ferguson:
Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits. ITC 1997: 597-606 - [c19]David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess, Jayashree Saxena, Kenneth M. Butler:
Bridging Fault Diagnosis in the Absence of Physical Information. ITC 1997: 887-893 - 1996
- [j7]Haluk Konuk, F. Joel Ferguson, Tracy Larrabee:
Charge-based fault simulation for CMOS network breaks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1555-1567 (1996) - [c16]Haluk Konuk, F. Joel Ferguson:
An unexpected factor in testing for CMOS opens: the die surface. VTS 1996: 422-429 - 1995
- [c15]Haluk Konuk, F. Joel Ferguson, Tracy Larrabee:
Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks. DAC 1995: 345-351 - [c14]Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee:
Diagnosis of realistic bridging faults with single stuck-at information. ICCAD 1995: 185-192 - 1994
- [c12]Brian Chess, Anthony Freitas, F. Joel Ferguson, Tracy Larrabee:
Testing CMOS Logic Gates for Realistic Shorts. ITC 1994: 395-402 - 1991
- [c6]F. Joel Ferguson, Tracy Larrabee:
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs. ITC 1991: 492-499 - [c5]F. Joel Ferguson, Tracy Larrabee:
Test pattern generation for current testable faults in static CMOS circuits. VTS 1991: 297-302 - 1990
- [c4]F. Joel Ferguson, Martin Taylor, Tracy Larrabee:
Testing for parametric faults in static CMOS circuits. ITC 1990: 436-443 - 1988
- [j3]F. Joel Ferguson, John Paul Shen:
A CMOS fault extractor for inductive fault analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(11): 1181-1194 (1988) - [c3]John Paul Shen, F. Joel Ferguson:
Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis. ITC 1988: 475-484 - 1985
- [j2]John Paul Shen, Wojciech Maly, F. Joel Ferguson:
Inductive Fault Analysis of MOS Integrated Circuits. IEEE Des. Test 2(6): 13-26 (1985) - 1984
- [j1]John Paul Shen, F. Joel Ferguson:
The Design of Easily Tastabel VLSI Array Multipliers. IEEE Trans. Computers 33(6): 554-560 (1984) - [c2]Wojciech Maly, F. Joel Ferguson, John Paul Shen:
Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells. ITC 1984: 390-399 - 1983
- [c1]F. Joel Ferguson, John Paul Shen:
The design of two easily-testable VLSI array multipliers. IEEE Symposium on Computer Arithmetic 1983: 2-9
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