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ORCIDITC 1997: Washington, DC, USA
- Proceedings IEEE International Test Conference 1997, Washington, DC, USA, November 3-5, 1997. IEEE Computer Society 1997, ISBN 0-7803-4209-7
Plenary
- James T. Healy:
Future Management of the Semiconductor Manufacturing Process. 10 - Colin M. Maunder:
Plug and Play or Plug and Pray: We Have a Right to Know It Will Work (Or Why It Won't). 11
Dynamic Current Testing
- Edward I. Cole Jr., Jerry M. Soden, Paiboon Tangyunyong, Patrick L. Candelaria, Richard W. Beegle, Daniel L. Barton, Christopher L. Henderson, Charles F. Hawkins:
Transient Power Supply Voltage (VDDT) Analysis for Detecting IC Defects. 23-31 - J. S. Beasley, S. Pour-Mozafari, D. Huggett, Alan W. Righter, C. J. Apodaca:
iDD Pulse Response Testing Applied to Complex CMOS ICs. 32-39 - James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan:
Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data. 40-49
Embedded Core Testing
- Indradeep Ghosh
, Niraj K. Jha, Sujit Dey:
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. 50-59 - Bahram Pouya, Nur A. Touba:
Modifying User-Defined Logic for Test Access to Embedded Cores. 60-68 - Lee Whetsel:
An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores. 69-78
ATE Hardware Improvements For High-Speed Test
- Takahiro J. Yamaguchi, Masahiro Ishida, Marco Tilgner, Dong Sam Ha:
An Efficient Method for Compressing Test Data. 79-88 - Robert Gage, Ben Brown, John Donaldson, Alexander Joffe:
Hardware Compression Speeds on Bitmap Fail Display. 89-93 - David C. Keezer, R. J. Wenzel:
Low-Cost ATE PinElectronics for Multigigabit-per-Second At-Speed Test. 94-100
MCM Systems Test
- Andrew Flint:
A Simulation-Based JTAG ATPG Optimized for MCMs. 101-105 - Thomas G. Foote, Dale E. Hoffman, William V. Huott, Timothy J. Koprowski, Bryan J. Robbins, Mary P. Kusko:
Testing the 400-MHz IBM Generation-4 CMOS Chip. 106-114 - Otto A. Torreiter, Ulrich Baur, Georg Goecke, Kevin Melocco:
Testing the Enterprise IBM System/390TM Multi Processor. 115-123
Unpowered Opens Lecture Series
- Ted T. Turner:
Capacitive Leadframe Testing. 124 - Chuck Robinson:
Analog AC Harmonic Method for Detecting Solder Opens. 125-126
IDDQ Testing
- Ralf Arnold, Markus Feuser, Horst-Udo Wedekind, Thorsten Bode:
Experiences with Implementation of IDDQ Test for Identification and Automotive Products. 127-135 - Antoni Ferré, Joan Figueras:
IDDQ Characterization in Submicron CMOS. 136-145 - Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins:
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs. 146-155 - Anne E. Gattiker, Wojciech Maly:
Current Signatures: Application. 156-165
Progress On Standards And Benchmarks
- Harry Hulvershorn:
1149.5: Now It's a Standard, So What? 166-173 - Adam Cron:
IEEE P1149.4-Almost a Standard. 174-182 - Bozena Kaminska, Karim Arabi, I. Bell, José L. Huertas, Bruce C. Kim, Adoración Rueda, Mani Soma, Prashant Goteti:
Analog and Mixed-Signal Benchmark Circuits-First Release. 183-190 - Yervant Zorian:
Test Requirements for Embedded Core-Based Systems and IEEE P1500. 191-199
Memory Test
- Theo J. Powell, Dan Cline, Francis Hii:
A 256Meg SDRAM BIST for Disturb Test Application. 200-208 - Jörg E. Vollrath:
Cell Signal Measurement for High-Density DRAMs. 209-216 - R. Dean Adams, Edmond S. Cooley, Patrick R. Hansen:
A Self-Test Circuit for Evaluating Memory Sense-Amplifier Signal. 217-225 - Ad J. van de Goor, Mike Lin:
The Implementation of Pseudo-Random Memory Tests on Commercial Memory Testers. 226-235
Test Synthesis
- Kelly A. Ockunzzi, Christos A. Papachristou:
Testability Enhancement for Behavioral Descriptions Containing Conditional Statements. 236-245 - Vivek Chickermane, Kamran Zarrineh:
Addressing Early Design-For-Test Synthesis in a Production Environment. 246-255 - Harbinder Singh, James Beausang, Girish Patankar:
A Symbolic Simulation-Based ANSI/IEEE Std 1149.1 Compliance Checker and BSDL Generator. 256-264 - Toshiharu Asaka, Masaaki Yoshida, Subhrajit Bhattacharya, Sujit Dey:
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs. 265-274
Unpowered Opens Lecture Series
- B. Karen McElfresh:
RF Introduction and Analog Junction Techniques for Finding Opens. 275 - Stig Oresjo:
Unpowered Opens Test with X-Ray Laminography. 276 - Douglas W. Raymond:
Finding Opens with Optics. 277
Microprocessor Test I
- Carol Stolicny, Richard Davies, Pamela McKernan, Tuyen Truong:
Manufacturing Pattern Development for the Alpha 21164 Microprocessor. 278-285 - Jeff Brauch, Jay Fleischman:
Design of Cache Test Hardware on the HP PA8500. 286-293 - Adrian Carbine, Derek Feltham:
Pentium® Pro Processor Design for Test and Debug. 294-303
Diagnosis & Failure Analysis Lecture Series
- Yeoh Eng Hong, Martin Tay Tiong We:
The Application of Novel Failure Analysis Techniques for Advanced Multi-Layered CMOS Devices. 304-309 - Christopher L. Henderson, Jerry M. Soden:
Signature Analysis for IC Diagnosis and Failure Analysis. 310-318 - Phil Nigh, Donato O. Forlenza, Franco Motika:
Application and Analysis of IDDQ Diagnostic Software. 319-327
Deterministic Bist
- Krishnendu Chakrabarty, Jian Liu, Minyao Zhu, Brian T. Murray:
Test Width Compression for Built-In Self Testing. 328-337 - Christophe Fagot, Patrick Girard, Christian Landrault:
On Using Machine Learning for Logic BIST. 338-346 - Gundolf Kiefer, Hans-Joachim Wunderlich:
Using BIST Control for Pattern Generation. 347-355
Components for MCMS: Known-Good-Die and Substrates
- Von-Kyoung Kim, Tom Chen, Mick Tegethoff:
ASIC Manufacturing Test Cost Prediction at Early Design Stage. 356-361 - Adit D. Singh, Phil Nigh, C. Mani Krishna:
Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study. 362-369 - K. E. Newman, David C. Keezer:
A Low-Cost Massively-Parallel Interconnect Test Method for MCM Substrates. 370-378
Mixed-Signal Seminar: Measurement Techniques
- Takahiro J. Yamaguchi, Mani Soma:
Dynamic Testing of ADCs Using Wavelet Transforms. 379-388 - Stephen K. Sunter, Naveena Nagi:
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST. 389-395 - Benoit Dufort, Gordon W. Roberts:
Signal Generation Using Periodic Single-and Multi-Bit Sigma-Delta Modulated Streams. 396-405
Microprocessor Test II
- R. Scott Fetherston, Imtiaz P. Shaik, Siyad C. Ma:
Testability Features of AMD-K6TM Microprocessor. 406-413 - Carol Pyron, Javier Prado, James Golab:
Next-Generation PowerPCTM Microprocessor Test Strategy Improvements. 414-423 - Michael Mateja, Alfred L. Crouch, Renny Eisele, Grady Giles, Dale Amason:
A Case Study of the Test Development for the 2nd Generation ColdFire® Microprocessors. 424-432
Diagnosis and Failure Analysis Lecture Series Panel
- W. Kent Fuchs:
Logic Diagnosis-Diversion or Necessity? 433 - Paul G. Ryan:
Logical Diagnosis Solutions Must Drive Yield Improvement. 434 - Jerry M. Soden, Christopher L. Henderson:
IC Diagnosis: Industry Issues. 435
Design for Delay Test
- Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar:
Design for Primitive Delay Fault Testability. 436-445 - Jacob Savir:
Scan Latch Design for Delay Test. 446-453 - Ramesh C. Tekumalla, Premachandran R. Menon:
Delay Testing with Clock Control: An Alternative to Enhanced Scan. 454-462
Concurrent Checking
- Osama K. Abu-Shahla, Ian M. Bell:
An On-Line Self-Testing Switched-Current Integrator. 463-470 - Alfred L. Burress, Parag K. Lala:
On-Line Testable Logic Desgin for FPGA Implementation. 471-478 - Charles E. Stroud, M. Ding, S. Seshadri, Ramesh Karri, I. Kim, Subhajit Roy, S. Wu:
A Parameterized VHDL Library for On-Line Testing. 479-488
Mixed-Signal Seminar: Measurements Using P1149.4
- Kenneth P. Parker, John E. McDermid, Rodney A. Browen, Kozo Nuriya, Katsuhiro Hirayama, Akira Matsuzawa:
Design, Fabrications and Use of Mixed-Signal IC Testability Structures. 489-498 - Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou:
Parasitic Effect Removal for Analog Measurement in P1149.4 Environment. 499-508 - José Machado da Silva, Ana C. Leão, José Silva Matos, José Carlos Alves:
Implementation of Mixed Current/Voltage Testing Using the IEEE P1149.4 Infrastructure. 509-517
High-Performance Probes and Sockets
- James J. Brandes:
High-Performance Production Test Contractors for Fine-Pitch Integrated Circuits. 518-526 - Nicholas Sporck:
A New Probe Card Technology Using Compliant MicrospringsTM. 527-532 - R. Dennis Bates:
The Search for the Universal Probe Card Solution. 533-538
BIST and DFT Economics
- Charles E. Stroud, Eric Lee, Miron Abramovici:
BIST-Based Diagnostics of FPGA Logic Blocks. 539-547 - Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski:
Scan-Encoded Test Pattern Generation for BIST. 548-556 - Sichao Wei, Pranab K. Nag, Ronald D. Blanton, Anne E. Gattiker, Wojciech Maly:
To DFT or Not to DFT? 557-566
On-Line Testing Techniques for VLSI
- Eberhard Böhl, Thomas Lindenkreuz, R. Stephan:
The Fail-Stop Controller AE11. 567-577 - Karim Arabi, Bozena Kaminska:
Design and Realization of an Accurate Built-In Current Sensor for On-Line Power Dissipation Measurement and IDDQ Testing. 578-586 - Cecilia Metra, Michele Favalli, Bruno Riccò:
On-Line Testing Scheme for Clock's Faults. 587-596
Defect Behavior, Test Efficiency and Fault Model Extension
- Haluk Konuk, F. Joel Ferguson:
Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits. 597-606 - Michel Renovell, Yves Bertrand:
Test Strategy Sensitivity to Defect Parameters. 607-616 - Gilbert Vandling, Thomas Bartenstein:
Fault Model Extension for Diagnosing Custom Cell Fails. 617-624
Mixed-Signal Seminar Panel: On-Chip 1149.4, What for?
- Stephen K. Sunter:
P1149.4-Problem or Solution for Mixed-Signal IC Design? 625
Board-Level Test Methods
- Mathieu Gagnon, Bozena Kaminska:
Optical Communication Channel Test Using BIST Approaches. 626-635 - William J. Hughes III:
System-Level Boundary-Scan in a Highly Integrated Switch. 636-639 - Jiun-Lang Huang, Kwang-Ting Cheng:
Analog Fault Diagnosis for Unpowered Circuit Boards. 640-648 - Bret A. Stewart:
Board Level Automated Fault Injection for Fault Coverage and Diagnostic Efficiency. 649-654
Software For New Test Strategies
- Robert E. Huston:
Pin Margin Analysis. 655-662 - Steve Westfall:
Memory Test-Debugging Test Vectors Without ATE. 663-669 - Lakshmikantha S. Prabhu, Daniel A. Rosenthal:
A DSP-Based Feedback Loop for Mixed-Signal VLSI Testing. 670-674 - Yuhai Ma, Wanchun Shi:
OLDEVDTP: A Novel Environment for Off-Line Debugging of VLSI Device Test Programs. 675-684
Design-For-Test Topics
- Richard McGowen, F. Joel Ferguson:
Incorporating Physical Design-for-Test into Routing. 685-693 - Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Parameterizable Testing Scheme for FIR Filters. 694-703 - Sridhar Narayanan, Ashutosh Das:
An Efficient Scheme to Diagnose Scan Chains. 704-713 - Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey:
Scan Synthesis for One-Hot Signals. 714-722
Sequential ATPG
- Elizabeth M. Rudnick, Janak H. Patel:
Putting the Squeeze on Test Sequences. 723-732 - M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor:
Sequential Test Generation with Advanced Illegal State Search. 733-742 - Raghuram S. Tupuri, Jacob A. Abraham:
A Novel Functional Test Generation Method for Processors Using Commercial ATPG. 743-752 - Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Testability Analysis and ATPG on Behavioral RT-Level VHDL. 753-759
Mixed-Signal Seminar: BIST/DFT
- Arnold Frisch, Thomas Almy:
HABIST: Histogram-Based Analog Built-In Self-Test. 760-767 - Thomas M. Bocek, Tuyen D. Vu, Mani Soma, Jason D. Moffatt:
Experimental Results for Current-Based Analog Scan. 768-775 - Benoît R. Veillette, Gordon W. Roberts:
On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops. 776-785 - Karim Arabi, Bozena Kaminska:
Oscillation Built-In Self Test (OBIST) Scheme for Functional and Structural Testing of Analog and Mixed-Signal Integrated Circuits. 786-795
Test Engineering Topics
- Bob Cometta, Jan Witte:
Low Current and Low Voltages-The High-End OP AMP Testing Challenge. 796-801 - Minh Quach, Kim Harper:
Real-Time In-situ Monitoring and Characterization of Production Wafer Probing Process. 802-808 - Weiyu Chen, Melvin A. Breuer, Sandeep K. Gupta:
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs. 809-818
Tools and Techniques for Defect Testing
- Rajesh Raina, Charles Njinda, Robert F. Molyneaux:
How Seriously Do You Take Your Possible-Detect Faults? 819-828 - Ajay Khoche, Erik Brunvand:
ACT: A DFT Tool for Self-Timed Circuits. 829-837 - James P. Cusey, Janak H. Patel:
BART: A Bridging Fault Test Generation for Sequential Circuits. 838-847
Specialized BIST Generators
- Seongmoon Wang, Sandeep K. Gupta:
DS-LFSR: A New BIST TPG for Low Heat Dissipation. 848-857 - J. Li, X. Sun, K. Soon:
Tree-Structured Linear Cellular Automata and Their Applications as PRPGs. 858-867 - Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian, Mihalis Psarakis:
An Effective BIST Scheme for Arithmetic Logic Units. 868-877
Advances in Digital Logic Diagnosis
- Srikanth Venkataraman, W. Kent Fuchs:
Diagnosis of Bridging Faults in Sequential Circuits Using Adaptive Simulation, State Storage, and Path-Tracing. 878-886 - David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess, Jayashree Saxena, Kenneth M. Butler:
Bridging Fault Diagnosis in the Absence of Physical Information. 887-893 - Janusz Rajski, Jerzy Tyszer:
Fault Diagnosis in Scan-Based BIST. 894-902
Mixed-Signal Seminar: Fault Modeling
- Ramakrishna Voorakaranam, Sudip Chakrabarti, Junwei Hou, Alfred V. Gomes, Sasikumar Cherubal, Abhijit Chatterjee, William H. Kao:
Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis. 903-912 - Chen-Yang Pan, Kwang-Ting Cheng:
Fault Macromodeling for Analog/Mixed-Signal Circuits. 913-922 - Abhijeet Kolpekwar, Ronald D. Blanton:
Development of a MEMS Testing Methodology. 923-931
New Frontiers in Test
- Mitch Aigner:
Embedded At-Speed Test Probe. 932-937 - Yukiya Miura:
An IDDQ Sensor Circuit for Low-Voltage ICs. 938-947 - Tony Savor, Rudolph E. Seviora:
Supervisors for Testing Non-Deterministically Specified Systems. 948-953
Design Verification and Diagnosis
- Li-C. Wang, Magdy S. Abadir:
A New Validation Methodology Combining Test and Formal Verification for PowerPCTM Microprocessor Arrays. 954-963 - Richard Raimi, James Lear:
Analyzing a PowerPCTM620 Microprocessor Silicon Failure Using Model Checking. 964-973 - Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng:
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. 974-981
Delay Fault Testing
- Soumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski:
Algorithms for Switch Level Delay Fault Simulation. 982-991 - Zhongcheng Li, Robert K. Brayton, Yinghua Min:
Efficient Identification of Non-Robustly Untestable Path Delay Faults. 992-997 - Tapan J. Chakraborty, Vishwani D. Agrawal:
Effective Path Selection for Delay Fault Testing of Sequential Circuits. 998-1003
Test Language Standards
- Gregory A. Maston:
Structuring STIL for Incremental Test Development. 1004-1010 - Peter Wohl, John A. Waicukauski:
A Unified Interface for Scan Test Generation Based on STIL. 1011-1019 - John W. Sheppard, Leslie A. Orlidge:
Artificial Intelligence Exchange and Service Tie to All Test Environments (AI-ESTATE)-A New Standard for System Diagnostics. 1020-1029
Advances in Probe Technology
- Dave Unzicker, Michael Bonham, Rey Rincon:
Advances in Probe Technology: Best Sessions of the'97 Southwest Test Workshop. 1030
Partial Scan Is Dead. Long Live Almost-Full Scan!
- Steven F. Oakland:
Why Would an ASIC Foundry Accept Anything Less than Full Scan? 1031 - Jeff Rearick:
The Case of Partial Scan. 1032 - Douglas W. Raymond, Dominic F. Haigh:
Why Automate Optical Inspection? 1033
Ethics, Professionalism, And Accountability - Does it Exist in Test?
- William R. Simpson:
Ethics, Professionalism and Accountability in Testing. 1034
Vision Systems For Board Test: Meeting Their Promise?
- Richard Pye:
Vision Inspection: Meeting the Promise? 1035 - Donald Burr:
Solder Paste Inspection: Process Control for Defect Reduction. 1036
So What Is An Optimal Test Mix? A Discussion Of The SEMATECH Methods Experiment
- Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken, Wojciech Maly:
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment. 1037-1038
Embedded Core Test Plug-N-Play: Is It Achievable?
- Thomas L. Anderson:
Thoughts on Core Integration and Test. 1039 - Rudy Garcia:
Embedded Core Test Plug-n-Play: Is It Achievable? 1040 - Lee Whetsel:
Test Access of TAP'ed & Non-TAP'ed Cores. 1041
On-Line Testing, Industrial Practice And Perspectives
- Michael Nicolaidis:
On-Line Testing for VLSI. 1042
Best Paper
- Anne Meixner, Jash Banik:
Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique. 1043-1052
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