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Pasquale Corsonello
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Publications
- 2015
- [j38]Marco Lanuzza, Pasquale Corsonello, Stefania Perri:
Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 388-391 (2015) - 2014
- [j36]Pasquale Corsonello, Marco Lanuzza, Stefania Perri:
Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates. Int. J. Circuit Theory Appl. 42(1): 65-70 (2014) - [j35]Fabio Frustaci, Marco Lanuzza, Stefania Perri, Pasquale Corsonello:
Analyzing noise robustness of wide fan-in dynamic logic gates under process variations. Int. J. Circuit Theory Appl. 42(5): 452-467 (2014) - [j34]Stefania Perri, Marco Lanuzza, Pasquale Corsonello:
Design of high-speed low-power parallel-prefix adder trees in nanometer technologies. Int. J. Circuit Theory Appl. 42(7): 731-743 (2014) - [j33]Pasquale Corsonello, Fabio Frustaci, Marco Lanuzza, Stefania Perri:
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5): 1456-1464 (2014) - 2012
- [j30]Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello:
Energy-efficient single-clock-cycle binary comparator. Int. J. Circuit Theory Appl. 40(3): 237-246 (2012) - [j28]Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello:
Comparative analysis of yield optimized pulsed flip-flops. Microelectron. Reliab. 52(8): 1679-1689 (2012) - [j26]Marco Lanuzza, Pasquale Corsonello, Stefania Perri:
Low-Power Level Shifter for Multi-Supply Voltage Designs. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 922-926 (2012) - 2010
- [j21]Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello:
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications. ACM Trans. Reconfigurable Technol. Syst. 4(1): 8:1-8:22 (2010) - [c33]Sumit Kansal, Marco Lanuzza, Pasquale Corsonello:
Impact of Random Process Variations on Different 65nm SRAM Cell Topologies. ICETET 2010: 703-706 - [c32]Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello:
A new low-power high-speed single-clock-cycle binary comparator. ISCAS 2010: 317-320 - [c31]Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello:
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics. ISVLSI 2010: 458-459 - [c30]Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello:
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. PATMOS 2010: 180-189 - 2009
- [j20]Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello:
Low-power split-path data-driven dynamic logic. IET Circuits Devices Syst. 3(6): 303-312 (2009) - [j19]Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala:
Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. J. Low Power Electron. 5(3): 326-338 (2009) - [j18]Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello:
Designing High-Speed Adders in Power-Constrained Environments. IEEE Trans. Circuits Syst. II Express Briefs 56-II(2): 172-176 (2009) - [c29]Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello:
An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications. ARC 2009: 74-84 - [c28]Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello:
New performance/power/area efficient, reliable full adder design. ACM Great Lakes Symposium on VLSI 2009: 493-498 - [c26]Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala:
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. VLSI Design 2009: 45-50 - 2008
- [c24]Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala:
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. PATMOS 2008: 297-306 - 2007
- [c21]Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala:
A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. AHS 2007: 119-126 - [c19]Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo:
Design and Implementation of a 90nm Low bit-rate Image Compression Core. DSD 2007: 383-389 - [c18]Marco Lanuzza, Stefania Perri, Pasquale Corsonello:
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing. SAMOS 2007: 159-168 - 2006
- [j11]Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo:
Low bit rate image compression core for onboard space applications. IEEE Trans. Circuits Syst. Video Technol. 16(1): 114-128 (2006) - 2005
- [j7]Stefania Perri, Marco Lanuzza, Pasquale Corsonello, Giuseppe Cocorullo:
A high-performance fully reconfigurable FPGA-based 2D convolution processor. Microprocess. Microsystems 29(8-9): 381-391 (2005) - [c13]Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello:
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. FPL 2005: 13-18 - [c12]Marco Lanuzza, Martin Margala, Pasquale Corsonello:
Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. ISLPED 2005: 161-166 - 2004
- [j5]Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo:
Variable precision arithmetic circuits for FPGA-based multimedia processors. IEEE Trans. Very Large Scale Integr. Syst. 12(9): 995-999 (2004)
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