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ORCIDJacob R. Minz
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2000 – 2009
- 2008
[c8]Jacob R. Minz, Xin Zhao, Sung Kyu Lim
:
Buffered clock tree synthesis for 3D ICs under thermal variations. ASP-DAC 2008: 504-509- 2007
- [j4]Eric Wong, Jacob R. Minz, Sung Kyu Lim:
Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2023-2034 (2007) - 2006
- [j3]Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim:
Profile-guided microarchitectural floor planning for deep submicron processor design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1289-1300 (2006) - [j2]Jacob R. Minz, Sung Kyu Lim:
Block-level 3-D Global Routing With an Application to 3-D Packaging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2248-2257 (2006) - [j1]Eric Wong, Jacob R. Minz, Sung Kyu Lim:
Multi-Objective Module Placement For 3-D System-On-Package. IEEE Trans. Very Large Scale Integr. Syst. 14(5): 553-557 (2006) - [c7]Jacob R. Minz, Somaskanda Thyagaraja, Sung Kyu Lim:
Optical routing for 3D system-on-package. DATE 2006: 337-338 - [c6]Eric Wong, Jacob R. Minz, Sung Kyu Lim:
Decoupling capacitor planning and sizing for noise and leakage reduction. ICCAD 2006: 395-400 - 2005
- [c5]Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh:
3D module placement for congestion and power noise reduction. ACM Great Lakes Symposium on VLSI 2005: 458-461 - [c4]Jacob R. Minz, Eric Wong, Sung Kyu Lim:
Reliability-aware floorplanning for 3D circuits. SoCC 2005: 81-82 - 2004
- [c3]Jacob R. Minz, Sung Kyu Lim:
Layer assignment for reliable system-on-package. ASP-DAC 2004: 31-37 - [c2]Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim:
Profile-guided microarchitectural floorplanning for deep submicron processor design. DAC 2004: 634-639 - [c1]Jacob R. Minz, Mohit Pathak, Sung Kyu Lim:
Net and Pin Distribution for 3D Package Global Routing. DATE 2004: 1410-1411
Coauthor Index
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