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ORCIDRupesh S. Shelar
- > Home > Persons > Rupesh S. Shelar
Publications
- 2011
[j5]Yifang Liu, Rupesh S. Shelar, Jiang Hu:
Simultaneous Technology Mapping and Placement for Delay Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 416-426 (2011)- 2008
- [c9]Yifang Liu, Rupesh S. Shelar, Jiang Hu:
Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. ICCAD 2008: 101-106 - [r1]Rupesh S. Shelar, Prashant Saxena:
Estimation of Routing Congestion. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [b1]Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar:
Routing Congestion in VLSI Circuits - Estimation and Optimization. Series on Integrated Circuits and Systems, Springer 2007, ISBN 978-0-387-30037-5, pp. I-XIV, 1-248 - 2006
- [j3]Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar
:
Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 625-636 (2006) - 2005
- [j2]Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang:
A predictive distributed congestion metric with application to technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 696-710 (2005) - [j1]Rupesh S. Shelar, Sachin S. Sapatnekar:
BDD decomposition for delay oriented pass transistor logic synthesis. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 957-970 (2005) - [c7]Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar:
An efficient technology mapping algorithm targeting routing congestion under delay constraints. ISPD 2005: 137-144 - 2004
- [c6]Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang:
A predictive distributed congestion metric and its application to technology mapping. ISPD 2004: 210-217 - 2002
- [c5]Rupesh S. Shelar, Sachin S. Sapatnekar:
Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits. IWLS 2002: 209-214 - [c4]Rupesh S. Shelar, Sachin S. Sapatnekar:
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. ASP-DAC/VLSI Design 2002: 87-92 - 2001
- [c3]Rupesh S. Shelar, Sachin S. Sapatnekar:
Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits. ICCAD 2001: 449-452
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