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2010 – 2019
- 2015
[j3]Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 507-516 (2015)- [j2]Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 62-II(3): 301-305 (2015) - [c4]Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. ESSCIRC 2015: 96-99 - 2014
- [c3]Chih-Wen Yang, Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes. ISCAS 2014: 409-412 - 2012
- [c2]Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Stochastic decoding for LDPC convolutional codes. ISCAS 2012: 2621-2624 - 2010
- [j1]Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang:
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. J. Low Power Electron. 6(4): 551-562 (2010) - [c1]Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee:
A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique. APCCAS 2010: 1203-1206
Coauthor Index
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