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ORCIDJavier J. Sieiro
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Journal Articles
- 2020
[j9]Fábio Passos
, Elisenda Roca, Ricardo Martins, Nuno Lourenço, Saiyd Ahyoune, Javier J. Sieiro, Rafael Castro-López, Nuno Horta, Francisco V. Fernández:
Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology. IEEE Access 8: 51601-51609 (2020)- [j8]Fábio Passos, Elisenda Roca, Javier J. Sieiro, Rafaella Fiorelli, Rafael Castro-López, José María López-Villegas, Francisco V. Fernández:
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 560-571 (2020) - 2019
- [j7]Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta:
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 989-1002 (2019) - 2018
- [j6]Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández:
Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator. Integr. 63: 332-341 (2018) - 2017
- [j5]Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Javier J. Sieiro, José María López-Villegas, Neus Vidal:
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 15-26 (2017) - 2016
- [j4]Elisenda Roca, Javier J. Sieiro:
Introduction to the special issue on Radio Frequency Integrated Circuits (RFIC) design techniques. Integr. 52: 183-184 (2016) - 2014
- [j3]Reinier Gonzalez-Echevarria, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Javier J. Sieiro, Neus Vidal, José María López-Villegas:
Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(8): 1269-1273 (2014) - 2010
- [j2]Ignacio Gil, Ignasi Cairó, Javier J. Sieiro, José María López-Villegas:
Low-power current-reused RF front-end based on optimized transformers topology. Integr. 43(2): 230-236 (2010) - 2009
- [j1]Tomás Carrasco Carrillo, José Gabriel Macias-Montero, Aitor Osorio Martí, Javier Sieiro Córdoba, José María López-Villegas:
CMOS single-ended-to-differential low-noise amplifier. Integr. 42(3): 304-311 (2009)
Conference and Workshop Papers
- 2018
- [c4]Arnau Salas Barenys, Neus Vidal, Javier J. Sieiro, José María López-Villegas, B. Medina-Rodriguez, F. M. Ramos:
Fabrication of Full-3D Printed Electronics RF Passive Components and Circuits. PRIME 2018: 265-268 - 2017
- [c3]Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández:
Extending the frequency range of quasi-static electromagnetic solvers. SMACD 2017: 1-4 - 2012
- [c2]David Gascon, Andreu Sanuy, Javier J. Sieiro:
Compact class-AB follower for wideband closed loop line drivers. ICECS 2012: 101-104 - 2010
- [c1]Ignacio Gil, Raúl Fernández, Javier J. Sieiro, José María López-Villegas:
Optimized passive devices for low-power LNA design. ICECS 2010: 90-93
Coauthor Index
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