default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIntegration, Volume 43
Volume 43, Number 1, January 2010
- Lech Józwiak, Nadia Nedjah
, Miguel E. Figueroa:
Modern development methods and tools for embedded reconfigurable systems: A survey. 1-33
- Amir Kaivani, Ghassem Jaberipur:
Fully redundant decimal addition and subtraction using stored-unibit encoding. 34-41 - Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou:
Fast modulo 2n+1 multi-operand adders and residue generators. 42-48 - Roger Kahn, Shlomo Weiss:
Reducing leakage power with BTB access prediction. 49-57 - Rajdeep Mukhopadhyay, Anvesh Komuravelli, Pallab Dasgupta, Subrat Kumar Panda, Siddhartha Mukhopadhyay:
A static verification approach for architectural integration of mixed-signal integrated circuits. 58-71 - José M. Granado Criado, Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido:
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration. 72-80 - Bin Zhou, Yizheng Ye, Zhao-lin Li, Jianwei Zhang, Xin-chun Wu, Rui Ke:
A test set embedding approach based on twisted-ring counter with few seeds. 81-100 - Zhi Yang, Guangsheng Ma, Shu Zhang:
Formal verification of high-level data-flow synthesis designs using relational modeling and symbolic computation. 101-112 - Chiou-Yng Lee:
Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2m). 113-123 - Achutavarrier Prasad Vinod, Edmund Ming-Kit Lai, Douglas L. Maskell, Pramod Kumar Meher:
An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth. 124-135 - Manuel F. M. Barros, Jorge Guilherme, Nuno Horta:
Analog circuits optimization based on evolutionary computation techniques. 136-155 - Ruijing Shen, Sheldon X.-D. Tan, Ning Mi, Yici Cai:
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. 156-165
- Manel Puig, José María López-Villegas, Atila Herms:
Erratum to the Special Section on DCIS 2006 [Integration, the VLSI Journal, Volume 42, Issue 3, June 2009]. 166
Volume 43, Number 2, April 2010
- Duo Li, Sheldon X.-D. Tan:
Statistical analysis of large on-chip power grid networks by variational reduction scheme. 167-175 - Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi:
Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability. 176-187 - Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Wave-pipelined intra-chip signaling for on-FPGA communications. 188-201 - Charles Thangaraj, Alkan Cengiz, Tom Chen:
Rapid design space exploration using legacy design data and technology scaling trend. 202-219 - Naifeng Jing, Weifeng He, Yongxin Zhu, Zhigang Mao:
Statistical estimation and evaluation for communication mapping in Network-on-Chip. 220-229 - Ignacio Gil, Ignasi Cairó, Javier J. Sieiro, José María López-Villegas:
Low-power current-reused RF front-end based on optimized transformers topology. 230-236 - Bassel Soudan:
Reducing signal timing variations in inter-core busses. 237-249
Volume 43, Number 3, June 2010
- Juan M. Carrillo, Guido Torelli, Raquel Pérez-Aloe, José M. Valverde, J. Francisco Duque-Carrillo:
Single-pair bulk-driven CMOS input stage: A compact low-voltage analog cell for scaled technologies. 251-257 - Vibhuti B. Dave, Erdal Oruklu, Jafar Saniie:
Constant addition with flagged binary adder architectures. 258-267 - Ahmad Patooghy, Seyed Ghassem Miremadi, Mahdi Fazeli:
A low-overhead and reliable switch architecture for Network-on-Chips. 268-278 - Adnan Kabbani:
Logical effort based dynamic power estimation and optimization of static CMOS circuits. 279-288 - Soumya Pandit, Chittaranjan A. Mandal, Amit Patra:
An automated high-level topology generation procedure for continuous-time SigmaDelta modulator. 289-304 - Kai Liu, Yu Zhou, Yunsong Li, Jian Feng Ma:
A high performance MQ encoder architecture in JPEG2000. 305-317 - Yici Cai, Jin Shi, Shuai Li:
Optimization of via distribution and stacked via in multi-layered P/G networks. 318-325
Volume 43, Number 4, September 2010
- José L. Ayala, Arvind Sridhar, David Cuesta:
Thermal modeling and analysis of 3D multi-processor chips. 327-341
- Xu He, Sheqin Dong, Yuchun Ma:
Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs. 342-352 - Jiying Xue, Tao Li, Yangdong Deng, Zhiping Yu:
Full-chip leakage analysis for 65 nm CMOS technology and beyond. 353-364 - Meysam Zargham, Christian Schlegel, Jorge Pérez Chamorro, Cyril Lahuec, Fabrice Seguin, Michel Jézéquel, Vincent C. Gaudet:
Scaling of analog LDPC decoders in sub-100 nm CMOS processes. 365-377 - Song Chen, Takeshi Yoshimura:
Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints. 378-388
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-04 01:27 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
