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2010 – 2019
- 2018
[j6]Yong Ping Xu
, Tai-Haur Kuo, Matt Straayer, Harish Krishnaswamy, Arun Natarajan:
Introduction to the Special Issue on the 2018 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 53(12): 3343-3346 (2018)- [c8]Matt Straayer, Seung-Tak Ryu, Un-Ku Moon:
Session 14 overview: High-resolution ADCs: Data converter subcommittee. ISSCC 2018: 228-229 - 2017
- [c7]Harry Lee, Matt Straayer, Chris Mangelsdorf:
EE6: Return of survey says! ISSCC 2017: 525 - 2016
- [c6]Matt Straayer, Jim Bales, Dwight Birdsall, Denis C. Daly, Phillip Elliott, Bill Foley, Roy Mason, Vikas Singh, Xuejin Wang:
27.5 A 4GS/s time-interleaved RF ADC in 65nm CMOS with 4GHz input bandwidth. ISSCC 2016: 464-465 - [c5]Harry Lee, Matt Straayer, Chris Mangelsdorf:
EE3: Survey says! ISSCC 2016: 520 - 2015
- [c4]Seung-Tak Ryu, Matt Straayer:
Session 15 overview: Data-converter techniques: Data converters subcommittee. ISSCC 2015: 270-271 - 2014
- [j5]Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer:
A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration. IEEE J. Solid State Circuits 49(6): 1366-1382 (2014) - [c3]Dong-Young Chang, Carlos E. Muñoz, Denis C. Daly, Soon-Kyun Shin, Kevin Guay, Thomas Thurston, Hae-Seung Lee, Kush Gulati, Matthew Z. Straayer:
11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR. ISSCC 2014: 204-205 - 2012
- [c2]Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer:
A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS. CICC 2012: 1-4
2000 – 2009
- 2009
- [j4]Matthew Z. Straayer, Michael H. Perrott:
A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping. IEEE J. Solid State Circuits 44(4): 1089-1098 (2009) - 2008
- [b1]Matthew Z. Straayer:
Noise shaping techniques for analog and time to digital converters using voltage controlled oscillators. Massachusetts Institute of Technology, Cambridge, MA, USA, 2008 - [j3]Matthew Z. Straayer, Michael H. Perrott:
A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer. IEEE J. Solid State Circuits 43(4): 805-814 (2008) - [j2]Belal Helal, Matthew Z. Straayer, Gu-Yeon Wei, Michael H. Perrott:
A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance. IEEE J. Solid State Circuits 43(4): 855-863 (2008) - [j1]Chun-Ming Hsu, Matthew Z. Straayer, Michael H. Perrott:
A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation. IEEE J. Solid State Circuits 43(12): 2776-2786 (2008) - [c1]Chun-Ming Hsu, Matthew Z. Straayer, Michael H. Perrott:
A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation. ISSCC 2008: 340-341
Coauthor Index
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