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Henry Hsieh
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2020 – today
- 2021
- [c4]HsinChen Chen, Rolf Lagerquist, Ashish Nayak, Hugh Mair, Gokulakrishnan Manoharan, Ericbill Wang, Gordon Gammie, Efron Ho, Anand Rajagopalan, Lee-Kee Yong, Ramu Madhavaram, Madhur Jagota, Chi-Jui Chung, Sudhakar Maruthi, Jenny Wiedemeier, Tao Chen, Henry Hsieh, Daniel Dia, Amjad Sikiligiri, Manzur Rahman, Barry Chen, Curtis Lin, Vincent Lin, Elly Chiang, Cheng-Yuh Wu, Po-Yang Hsu, Jason Tsai, Wade Wu, Achuta Thippana, S. A. Huang:
A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor Subsystem. ISSCC 2021: 54-56
2010 – 2019
- 2015
- [j1]Brian Van Essen, Henry Hsieh, Sasha Ames, Roger A. Pearce, Maya B. Gokhale:
DI-MMAP - a scalable memory-map runtime for out-of-core data-intensive applications. Clust. Comput. 18(1): 15-28 (2015) - [c3]Henry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang:
Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology. CICC 2015: 1-3 - 2014
- [c2]Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang:
A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. CICC 2014: 1-4 - 2012
- [c1]Brian Van Essen, Henry Hsieh, Sasha Ames, Maya B. Gokhale:
DI-MMAP: A High Performance Memory-Map Runtime for Data-Intensive Applications. SC Companion 2012: 731-735
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