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Chiang-Hsiang Liao

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2010 – 2019

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2016
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  - journals/tvlsi/WangWLC16
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  - https://dblp.org/rec/journals/tvlsi/WangWLC16
Chua-Chin Wang, Deng-Shian Wang, Chiang-Hsiang Liao, Sih-Yu Chen:
A Leakage Compensation Design for Low Supply Voltage SRAM. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1761-1769 (2016)
2014
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Chua-Chin Wang, Chiang-Hsiang Liao, Sih-Yu Chen:
A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40 nm CMOS process. ISCAS 2014: 1126-1129

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