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ORCIDViv A. Bartlett
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2020 – today
- 2021
[j6]Sachin Maheshwari
, Viv A. Bartlett, Izzet Kale:
A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1721-1725 (2021)- 2020
- [j5]Himadri Singh Raghav, V. A. Bartlett:
Investigating the influence of adiabatic load on the 4-phase adiabatic system design. Integr. 75: 150-157 (2020)
2010 – 2019
- 2019
- [j4]Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale:
Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach. Integr. 67: 144-154 (2019) - 2018
- [j3]Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale:
Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication. Integr. 62: 341-352 (2018) - [j2]Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale:
Investigating the effectiveness of Without Charge-Sharing Quasi-Adiabatic Logic for energy efficient and secure cryptographic implementations. Microelectron. J. 76: 8-21 (2018) - [c9]Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale:
Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard Applications. PATMOS 2018: 39-45 - [c8]Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale:
VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design. PATMOS 2018: 111-117 - 2017
- [c7]Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale:
Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers. ECCTD 2017: 1-4 - [c6]Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale:
A novel power analysis attack resilient adiabatic logic without charge sharing. ECCTD 2017: 1-4 - [c5]Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale:
Robustness of power analysis attack resilient adiabatic logic: WCS-QuAL under PVT variations. PATMOS 2017: 1-8 - 2016
- [c4]Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale:
Energy efficiency of 2-step charging power-clock for adiabatic logic. PATMOS 2016: 176-182
2000 – 2009
- 2001
- [j1]V. A. Bartlett, Eckhard Grass:
Exploiting Data-dependencies in Ultra Low-power DSP Arithmetic. VLSI Design 12(3): 349-363 (2001) - [c3]V. A. Bartlett, Eckhard Grass:
A Low-Power Asynchronous VLSI FIR Filter. ARVLSI 2001: 29-41 - [c2]Viv A. Bartlett, Andrew G. Dempster:
Using carry-save adders in low-power multiplier blocks. ISCAS (4) 2001: 222-225
1990 – 1999
- 1999
- [c1]V. A. Bartlett, Eckhard Grass:
A low-power concurrent multiplier-accumulator using conditional evaluation. ICECS 1999: 629-633
Coauthor Index
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