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ORCIDVLSI Design, Volume 12
Volume 12, Number 1, 2001
- Jun Dong Cho
, Jin Youn Cho:
Deep-submicron Placement Minimizing Crosstalk. 1-12 - John Marty Emmert, Dinesh K. Bhatia:
Two-dimensional Placement Using Tabu Search. 13-23 - Taras I. Golota, Sotirios G. Ziavras:
A Universal, Dynamically Adaptable and Programmable Network Router for Parallel Computers. 25-52 - Edward Y. C. Cheng, Sartaj K. Sahni:
A Fast Algorithm for Transistor Folding. 53-60 - Shih-Chang Hsia, Chien-Cheng Tseng:
A Size-optimization Design for Variable Length Coding Using Distributed Logic. 61-68 - George Theodoridis, Spyros Theoharis, Dimitrios Soudris, Constantinos E. Goutis:
A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model. 69-79 - C. P. Ravikumar, Vikas Jain, Anurag Dod:
Distributed Fault Simulation Algorithms on Parallel Virtual Machine. 81-99
Volume 12, Number 2, 2001
- Jun-Dong Cho:
Preface. - Koen Danckaert, Chidamber Kulkarni, Francky Catthoor, Hugo De Man, Vivek Tiwari:
A Systematic Approach to Reduce the System Bus Load and Power in Multimedia Algorithms. 101-111 - Mao-Hsu Yen, Sao-Jie Chen, Sanko Lan:
Symmetric and Programmable Multi-Chip Module for Low-Power Prototyping System. 113-124 - Anshuman Nayak, Malay Haldar, Prith Banerjee, Chunhong Chen, Majid Sarrafzadeh:
Power Optimization of Delay Constrained Circuits. 125-138 - Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai:
Power-conscious Scheduling for Real-time Embedded Systems Design. 139-150 - G. Esakkimuthu, Hyun Suk Kim, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Investigating Memory System Energy Behavior Using Software and Hardware Optimizations. 151-165 - Bengt Oelmann, Kalle Tammemäe, Margus Kruus, Mattias O'Nils:
Automatic FSM Synthesis for Low-power Mixed Synchronous/Asynchronous Implementation. 167-186 - Miriam E. Leeser, Valerie Ohm:
Accurate Power Estimation for Sequential CMOS Circuits Using Graph-based Methods. 187-203 - George Theodoridis, S. Theoharis, Dimitrios Soudris, Constantinos E. Goutis:
A Fast and Accurate Method of Power Estimation for Logic Level Networks. 205-219 - Jung Yun Choi, Young Hwan Kim, Kyoung-Rok Cho:
Backward Propagated Capacitance Model for Register Transfer Level Power Estimation. 221-231 - Lih-Yih Chiou, Khurram Muhammad, Kaushik Roy:
Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications. 233-243 - Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Sarta:
An Instruction-Level Power Analysis Model with Data Dependency. 245-273 - Akhilesh Tyagi:
Integrated Area-power Optimal State Assignment. 275-300
Volume 12, Number 3, 2001
- Jun-Dong Cho:
Preface. - Koon-Shik Cho, Jun-Dong Cho:
Low Power Digital Multimedia Telecommunication Designs. 301-315 - Alvar Dean, David Garrett, Mircea R. Stan, Sebastian Ventrone:
Low Power Design for ASIC Cores. 317-331 - Mike J. G. Lewis, Linda E. M. Brackenbury:
CADRE: A Low-power, Low-EMI DSP Architecture for Digital Mobile Phones. 333-348 - V. A. Bartlett, Eckhard Grass:
Exploiting Data-dependencies in Ultra Low-power DSP Arithmetic. 349-363 - Martin Kuhlmann, Keshab K. Parhi:
A Novel Low-power Shared Division and Square-root Architecture Using the GST Algorithm. 365-376 - Rong Lin:
A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits. 377-390 - Jun-Mo Jung, Jong-Wha Chong:
A Low Power FIR Filter Design for Image Processing. 391-397 - Geun Rae Cho, Tom Chen:
On Mixed PTL/Static Logic for Low-power and High-speed Circuits. 399-406 - Esther Rodríguez-Villegas, Alberto Yufera, Adoración Rueda:
A Low-Voltage Floating-Gate MOS Biquad. 407-414 - Abdoul Rjoub, Odysseas G. Koufopavlou:
Efficient Low Power/Low Swing Bus Design Architectures. 415-429 - Dimitris Bakalis, Xrysovalantis Kavousianos, Haridimos T. Vergos, Dimitris Nikolos, G. Ph. Alexiou:
Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. 431-448 - Yongha Lee, Jongho Choi, Gyu Moon, Jeomkeun Kim:
Simultaneous Switching Noise Minimization Technique Using Dual Layer Power Line Mutual Inductors. 449-455
Volume 12, Number 4, 2001
- Sunil R. Das:
Guest Editorial. - Wen-Ben Jone, Der-Cheng Huang, Shih-Chieh Chang, Sunil R. Das:
Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis. 457-474 - Anshuman Chandra, Krishnendu Chakrabarty, Mark C. Hansen:
Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters. 475-486 - Jacob Savir:
BIST-Based Fault Diagnosis in the Presence of Embedded Memories. 487-500 - Xiaomei Liu, Prachi Sathe, Samiha Mourad:
Effect of Reverse Body Bias on Current Testing of 0.18 μm Gates. 501-513 - Jacob Savir:
Test Generators Need to be Modified to Handle CMOS Designs. 515-525 - Parag K. Lala, Alvernon Walker:
A Fine Grain Configurable Logic Block for Self-checking FPGAs. 527-536 - Shih-Chieh Chang, Kwen-Yo Chen, Ching-Hsiang Cheng, Wen-Ben Jone, Sunil R. Das:
Random Pattern Testability Enhancement by Circuit Rewiring. 537-549 - B. K. S. V. L. Varaprasad, L. M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal:
An Efficient Test Pattern Generation Scheme for an On Chip BIST. 551-562 - Jacob Savir:
BIST Analysis of an Embedded Memory Associated Logic. 563-578
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