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Rabindra K. Roy
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2000 – 2009
- 2000
- [j15]T. Karn, Shishpal Rawat, Desmond Kirkpatrick, Rabindra K. Roy, Gregory S. Spirakis, Naveed A. Sherwani, Craig Peterson:
EDA challenges facing future microprocessor design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(12): 1498-1506 (2000)
1990 – 1999
- 1999
- [j14]Huy Nguyen, Rabindra K. Roy, Abhijit Chatterjee:
Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits. J. Electron. Test. 14(3): 259-272 (1999) - [c26]Unni Narayanan, Georgios I. Stamoulis, Rabindra K. Roy:
Characterizing Individual Gate Power Sensitivity in Low Power Design. VLSI Design 1999: 625- - 1998
- [j13]Srivaths Ravi, Indradeep Ghosh
, Rabindra K. Roy, Sujit Dey:
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. J. Electron. Test. 13(2): 201-212 (1998) - [j12]Huy T. Nguyen, Abhijit Chatterjee, Rabindra K. Roy:
Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis. J. VLSI Signal Process. 18(1): 25-38 (1998) - [c25]Sujit Dey, Anand Raghunathan, Rabindra K. Roy:
Considering Testability during High-level Design (Embedded Tutorial). ASP-DAC 1998: 205-210 - [c24]Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey:
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. VLSI Design 1998: 193-198 - [c23]Huy Nguyen, Rabindra K. Roy, Abhijit Chatterjee:
Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential Circuits. VLSI Design 1998: 199-204 - 1997
- [j11]Abhijit Chatterjee, Rabindra K. Roy:
Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization. IEEE Trans. Computers 46(11): 1208-1218 (1997) - [c22]Kaushik Roy, Rabindra K. Roy, Ramesh Harjani, K. S. Murthy:
T5: Low-Power Design. VLSI Design 1997: 4 - [c21]Huy Nguyen, Abhijit Chatterjee, Rabindra K. Roy:
Impact of Partial Reset on Fault Independent Testing and BIST. VLSI Design 1997: 537-539 - 1996
- [j10]Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar:
Initialization issues in asynchronous circuit synthesis. J. Electron. Test. 9(3): 237-250 (1996) - [j9]Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan:
Synthesis of initializable asynchronous circuits. IEEE Trans. Very Large Scale Integr. Syst. 4(2): 254-263 (1996) - [c20]Savita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy:
Synchronous Test Generation Model for Asynchronous Circuits. VLSI Design 1996: 178-185 - 1995
- [j8]Tam-Anh Chu, Rabindra K. Roy:
Guest Editors' Introduction: More Practical Asynchronous Design. IEEE Des. Test Comput. 12(1): 13- (1995) - [j7]Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy:
Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5): 531-546 (1995) - [j6]Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy:
Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1141-1154 (1995) - [c19]Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy:
Synthesis-for-testability using transformations. ASP-DAC 1995 - [c18]Rabindra K. Roy:
Advantages of High-Level Test Synthesis over Design for Test. ITC 1995: 293 - 1994
- [j5]Tam-Anh Chu, Rabindra K. Roy:
Guest Editor's Introduction: Practical Asynchronous Design. IEEE Des. Test Comput. 11(2): 6-7 (1994) - [c17]Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan:
Signal Transition Graph Transformations for Initializability. EDAC-ETC-EUROASIC 1994: 670 - [c16]Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy:
Behavioral synthesis of low-cost partial scan designs for DSP applications. ICASSP (2) 1994: 441-444 - [c15]Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan:
Initialization Isuues in the Synthesis of Asynchronous Circuits. ICCD 1994: 447-452 - [c14]Abhijit Chatterjee, Rabindra K. Roy:
Synthesis of Low Power Linear DSP Circuits Using Activity Metrics. VLSI Design 1994: 265-270 - [c13]Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan:
Synthesis of Initializable Asynchronous Circuits. VLSI Design 1994: 383-388 - [c12]Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy:
Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application. VTS 1994: 2-7 - [c11]Abhijit Chatterjee, Rabindra K. Roy:
Design for diagnosability of linear digital filters using time-space expansion. VTS 1994: 48-53 - 1993
- [j4]Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu:
Greedy hardware optimization for linear digital circuits using number splitting and refactorization. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 423-431 (1993) - [c10]Abhijit Chatterjee, Rabindra K. Roy:
An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition. DAC 1993: 343-348 - [c9]Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy:
Exploiting hardware sharing in high-level synthesis for partial scan optimization. ICCAD 1993: 20-25 - [c8]Abhijit Chatterjee, Rabindra K. Roy:
Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters. ICCD 1993: 606-609 - [c7]Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu:
Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting. VLSI Design 1993: 154-159 - 1992
- [j3]Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham:
Test compaction for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(2): 260-267 (1992) - [j2]Miron Abramovici, David T. Miller, Rabindra K. Roy:
Dynamic redundancy identification in automatic test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(3): 404-407 (1992) - [c6]Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu:
Automatic test generation for linear digital systems with bi-level search using matrix transform methods. ICCAD 1992: 224-228 - [c5]Rabindra K. Roy, Naveena Nagi, Abhijit Chatterjee, Manuel A. d'Abreu:
Delay fault testing of iterative arithmetic arrays. VTS 1992: 25-30 - 1991
- [j1]Abhijit Chatterjee, Rabindra K. Roy, Jacob A. Abraham, Janak H. Patel:
Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors. Digit. Signal Process. 1(4): 231-244 (1991) - [c4]Miron Abramovici, James J. Kulikowski, Rabindra K. Roy:
The Best Flip-Flops to Scan. ITC 1991: 166-173 - 1990
- [b1]Rabindra K. Roy:
Timing verification and synthesis of circuits for delay fault testability. University of Illinois Urbana-Champaign, USA, 1990
1980 – 1989
- 1989
- [c3]Miron Abramovici, David T. Miller, Rabindra K. Roy:
Dynamic redundancy identification in automatic test generation. ICCAD 1989: 466-469 - 1988
- [c2]Patrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers:
Fault Simulation in a Distributed Environment. DAC 1988: 686-691 - [c1]Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh:
Compaction of ATPG-generated test sequences for sequential circuits. ICCAD 1988: 382-385
Coauthor Index
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