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ORCIDMasayuki Sato 0001
Person information
- affiliation: Tohoku University, Sendai, Japan
Other persons with the same name
- Masayuki Sato — disambiguation page
- Masayuki Sato 0002 — Gunma University, Department of Bio-Chemical Engineering, Japan
- Masayuki Sato 0003
![[0000-0003-0387-3467]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0003-0387-3467")
— Japan Aerospace Exploration Agency, Institute of Space Technology and Aeronautics, Tokyo, Japan (and 1 more)
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2020 – today
- 2023
[j14]Masahito Kumagai, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi:
Ising-Based Kernel Clustering. Algorithms 16(4): 214 (2023)- [j13]Bin Qi, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi:
A dynamic parameter tuning method for SpMM parallel execution. Concurr. Comput. Pract. Exp. 35(17) (2023) - [j12]Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi:
An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture. IEICE Trans. Electron. 106(6): 312-320 (2023) - [c42]Yihui Liu, Kazuhiko Komatsu, Masahito Kumagai, Masayuki Sato, Hiroaki Kobayashi:
Performance Evaluation of Tsunami Evacuation Route Planning on Multiple Annealing Machines. CF 2023: 185-188 - [c41]Chunting Duan, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi:
Multi-scale Loss based Electron Microscopic Image Pair Matching Method. ICMLA 2023: 1949-1956 - [c40]Yusuke Fukasawa, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi:
Appropriate Graph-Algorithm Selection for Edge Devices Using Machine Learning. MCSoC 2023: 544-551 - [c39]Makoto Onoda, Kazuhiko Komatsu, Masahito Kumagai, Masayuki Sato, Hiroaki Kobayashi:
A Constraint Partition Method for Combinatorial Optimization Problems. MCSoC 2023: 600-607 - 2022
- [j11]Shunsuke Tsukada, Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi:
A Metadata Prefetching Mechanism for Hybrid Memory Architectures. IEICE Trans. Electron. 105-C(6): 232-243 (2022) - [c38]Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi:
An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture. COOL CHIPS 2022: 1-3 - [c37]Masayuki Sato, Yuya Omori, Ryusuke Egawa, Ken Nakamura, Daisuke Kobayashi, Hiroe Iwasaki, Kazuhiko Komatsu, Hiroaki Kobayashi:
A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders. PDCAT 2022: 288-300 - [c36]Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi:
Page-Address Coalescing of Vector Gather Instructions for Efficient Address Translation. IA3@SC 2022: 1-8 - 2021
- [j10]Hao Tang, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi:
Efficient Mixed-Precision Tall-and-Skinny Matrix-Matrix Multiplication for GPUs. Int. J. Netw. Comput. 11(2): 267-282 (2021) - [j9]Masahito Kumagai, Kazuhiko Komatsu, Fumiyo Takano, Takuya Araki, Masayuki Sato, Hiroaki Kobayashi:
An External Definition of the One-Hot Constraint and Fast QUBO Generation for High-Performance Combinatorial Clustering. Int. J. Netw. Comput. 11(2): 463-491 (2021) - [j8]Kazuhiko Komatsu, Akito Onodera, Erich Focht, Soya Fujimoto, Yoko Isobe, Shintaro Momose, Masayuki Sato, Hiroaki Kobayashi:
Performance and Power Analysis of a Vector Computing System. Supercomput. Front. Innov. 8(2): 75-94 (2021) - [j7]Osamu Watanabe, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi:
Optimizing Load Balance in a Parallel CFD Code for a Large-scale Turbine Simulation on a Vector Supercomputer. Supercomput. Front. Innov. 8(2): 114-130 (2021) - [c35]Shunsuke Tsukada, Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi:
A Metadata Prefetching Mechanism for Hybrid Memory Architectures. COOL CHIPS 2021: 1-3 - [c34]Kazuhiko Komatsu, Masahito Kumagai, Ji Qi, Masayuki Sato, Hiroaki Kobayashi:
An Externally-Constrained Ising Clustering Method for Material Informatics. CANDAR (Workshops) 2021: 201-204 - [c33]Kou Murakami, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi:
A Processor Selection Method based on Execution Time Estimation for Machine Learning Programs. IPDPS Workshops 2021: 779-788 - [c32]Masahito Kumagai, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi:
Ising-Based Combinatorial Clustering Using the Kernel Method. MCSoC 2021: 197-203 - [c31]Zhilin He, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi:
Optimizations of a Linear Matrix Solver in a Composite Simulation for a Vector Computer. PAAP 2021: 33-37 - [c30]Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi:
Register Flush-free Runahead Execution for Modern Vector Processors. SBAC-PAD 2021: 114-125 - 2020
- [c29]Akito Onodera, Kazuhiko Komatsu, Soya Fujimoto, Yoko Isobe, Masayuki Sato, Hiroaki Kobayashi:
Optimization of the Himeno Benchmark for SX-Aurora TSUBASA. Bench 2020: 127-143 - [c28]Masayuki Sato, Xue Hao, Kazuhiko Komatsu, Hiroaki Kobayashi:
Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture. COOL CHIPS 2020: 1-3 - [c27]Masahito Kumagai, Kazuhiko Komatsu, Fumiyo Takano, Takuya Araki, Masayuki Sato, Hiroaki Kobayashi:
Combinatorial Clustering Based on an Externally-Defined One-Hot Constraint. CANDAR 2020: 59-68 - [c26]Hao Tang, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi:
An Efficient Skinny Matrix-Matrix Multiplication Method by Folding Input Matrices into Tensor Core Operations. CANDAR (Workshops) 2020: 164-167 - [c25]Takumi Kishitani, Kazuhiko Komatsu, Masayuki Sato, Akihiro Musa, Hiroaki Kobayashi:
Importance of Selecting Data Layouts in the Tsunami Simulation Code. IPDPS Workshops 2020: 830-837 - [c24]Yiran Cheng, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi:
A Deep Reinforcement Learning Based Feature Selector. PAAP 2020: 378-389 - [c23]Bin Qi, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi:
A Dynamic Parameter Tuning Method for High Performance SpMM. PDCAT 2020: 318-329
2010 – 2019
- 2019
- [j6]Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi:
A Skewed Multi-banked Cache for Many-core Vector Processors. Supercomput. Front. Innov. 6(3): 86-101 (2019) - [j5]Masayuki Sato, Takuya Toyoshima, Hikaru Takayashiki, Ryusuke Egawa, Hiroaki Kobayashi:
An Energy-aware Dynamic Data Allocation Mechanism for Many-channel Memory Systems. Supercomput. Front. Innov. 6(4): 4-19 (2019) - [c22]Masayuki Sato, Yongcheng Chen, Haruya Kikuchi, Kazuhiko Komatsu, Hiroaki Kobayashi:
Perceptron-based Cache Bypassing for Way-Adaptable Caches. COOL CHIPS 2019: 1-3 - [c21]Ryusuke Egawa, Ryoma Saito, Masayuki Sato, Hiroaki Kobayashi:
A Layer-Adaptable Cache Hierarchy by a Multiple-layer Bypass Mechanism. HEART 2019: 12:1-12:6 - [c20]Akihiro Musa, Takashi Abe, Takumi Kishitani, Takuya Inoue, Masayuki Sato, Kazuhiko Komatsu, Yoichi Murashima, Shunichi Koshimura, Hiroaki Kobayashi:
Performance Evaluation of Tsunami Inundation Simulation on SX-Aurora TSUBASA. ICCS (2) 2019: 363-376 - [c19]Kazuhiko Komatsu, Takumi Kishitani, Masayuki Sato, Hiroaki Kobayashi:
An Appropriate Computing System and Its System Parameters Selection Based on Bottleneck Prediction of Applications. IPDPS Workshops 2019: 768-777 - [c18]Osamu Watanabe, Yuta Hougi, Kazuhiko Komatsu, Masayuki Sato, Akihiro Musa, Hiroaki Kobayashi:
Optimizing Memory Layout of Hyperplane Ordering for Vector Supercomputer SX-Aurora TSUBASA. MCHPC@SC 2019: 25-32 - [c17]Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi:
A Hardware Prefetching Mechanism for Vector Gather Instructions. IA3@SC 2019: 59-66 - 2018
- [j4]Masayuki Sato, Yoshiki Shoji, Zentaro Sakai, Ryusuke Egawa, Hiroaki Kobayashi:
An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches. IEEE Trans. Multi Scale Comput. Syst. 4(4): 593-604 (2018) - [c16]Masayuki Sato, Zehua Li, Ryusuke Egawa, Hiroaki Kobayashi:
An energy-aware set-level refreshing mechanism for eDRAM last-level caches. COOL CHIPS 2018: 1-3 - [c15]Kazuhiko Komatsu, Takumi Kishitani, Masayuki Sato, Akihiro Musa, Hiroaki Kobayashi:
Search Space Reduction for Parameter Tuning of a Tsunami Simulation on the Intel Knights Landing Processor. MCSoC 2018: 117-124 - [c14]Kazuhiko Komatsu, Shintaro Momose, Yoko Isobe, Osamu Watanabe, Akihiro Musa, Mitsuo Yokokawa, Toshikazu Aoyama, Masayuki Sato, Hiroaki Kobayashi:
Performance evaluation of a vector supercomputer SX-aurora TSUBASA. SC 2018: 54:1-54:12 - 2017
- [c13]Masayuki Sato, Zentaro Sakai, Ryusuke Egawa, Hiroaki Kobayashi:
An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches. COOL Chips 2017: 1-2 - [c12]Takuya Toyoshima, Masayuki Sato, Ryusuke Egawa, Hiroaki Kobayashi:
An application-adaptive data allocation method for multi-channel memory. COOL Chips 2017: 1-3 - [c11]Jubee Tada, Masayuki Sato, Ryusuke Egawa:
An Adaptive Demotion Policy for High-Associativity Caches. HEART 2017: 4:1-4:6 - 2016
- [c10]Ryusuke Egawa, Wataru Uno, Masayuki Sato, Hiroaki Kobayashi, Jubee Tada:
A power-aware LLC control mechanism for the 3D-stacked memory system. 3DIC 2016: 1-4 - [c9]Masayuki Sato, Shin Nishimura, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
A cache partitioning mechanism to protect shared data for CMPs. COOL Chips 2016: 1-2 - 2015
- [j3]Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
FLEXII: A Flexible Insertion Policy for Dynamic Cache Resizing Mechanisms. IEICE Trans. Electron. 98-C(7): 550-558 (2015) - [c8]Masayuki Sato, Chengguang Han, Kazuhiko Komatsu, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
An energy-efficient dynamic memory address mapping mechanism. COOL Chips 2015: 1-3 - 2014
- [j2]Ye Gao, Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
MVP-Cache: A Multi-Banked Cache Memory for Energy-Efficient Vector Processing of Multimedia Applications. IEICE Trans. Inf. Syst. 97-D(11): 2835-2843 (2014) - [c7]Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
On-chip checkpointing with 3D-stacked memories. 3DIC 2014: 1-6 - [c6]Ye Gao, Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
An energy optimization method for vector processing mechanisms. COOL Chips 2014: 1-3 - 2013
- [j1]Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
A Capacity-Aware Thread Scheduling Method Combined with Cache Partitioning to Reduce Inter-Thread Cache Conflicts. IEICE Trans. Inf. Syst. 96-D(9): 2047-2054 (2013) - [c5]Ryusuke Egawa, Masayuki Sato, Jubee Tada, Hiroaki Kobayashi:
Vertically integrated processor and memory module design for vector supercomputers. 3DIC 2013: 1-6 - [c4]Masayuki Sato, Yusuke Tobo, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
A flexible insertion policy for dynamic cache resizing mechanisms. COOL Chips 2013: 1-3 - 2012
- [c3]Masayuki Sato, Yusuke Tobo, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
A capacity-efficient insertion policy for dynamic cache resizing mechanisms. Conf. Computing Frontiers 2012: 265-268 - 2010
- [c2]Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
A Majority-Based Control Scheme for Way-Adaptable Caches. Facing the Multicore-Challenge 2010: 16-28 - [c1]Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
A voting-based working set assessment scheme for dynamic cache resizing mechanisms. ICCD 2010: 98-105
Coauthor Index
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