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ORCIDZheng Yu 0001
Person information
- affiliation: Fudan University, State Key Lab of ASIC and System, Shanghai, China
Other persons with the same name
- Zheng Yu — disambiguation page
- Zheng Yu 0002 — Auckland University, New Zealand
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2010 – 2019
- 2014
[j2]Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming-e Jing, Xiaoyang Zeng:
A 16-Core Processor With Shared-Memory and Message-Passing Communications. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(4): 1081-1094 (2014)- [j1]Zheng Yu, Zhiyi Yu, Xueqiu Yu, Ningxi Liu, Xiaoyang Zeng:
Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process. IEEE Trans. Circuits Syst. II Express Briefs 61-II(6): 423-427 (2014) - 2013
- [c4]Shikai Zhu, Zheng Yu, Shile Cui, Zhiyi Yu, Xiaoyang Zeng:
H.264 video parallel decoder on a 24-core processor. ASICON 2013: 1-4 - [c3]Zheng Yu, Jiajie Zhang, Xueqiu Yu, Xiaoyang Zeng, Zhiyi Yu:
A low power register file with asynchronously controlled read-isolation and software-directed write-discarding. ISCAS 2013: 349-352 - [c2]Peng Ou, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu, Xueqiu Yu, Shile Cui, Jie Feng, Shikai Zhu, Jie Lin, Ming-e Jing, Xiaoyang Zeng, Zhiyi Yu:
A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array. ISSCC 2013: 56-57 - [c1]Jiajie Zhang, Zheng Yu, Zhiyi Yu, Kexin Zhang, Zhonghai Lu, Axel Jantsch:
Efficient distributed memory management in a multi-core H.264 decoder on FPGA. ISSoC 2013: 1-4
Coauthor Index
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