default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIEEE Transactions on Circuits and Systems - Part II: Express Briefs, Volume 61-II
Volume 61-II, Number 1, January 2014
- Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung:
Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector. 1-5 - Ghil-Geun Oh, Chang-Kyo Lee, Seung-Tak Ryu:
A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications. 6-10 - Guanhua Wang, Foti Kacani, Yun Chiu
:
IRD Digital Background Calibration of SAR ADC With Coarse Reference ADC Acceleration. 11-15 - I-Ting Lee, Shih-Han Ku, Shen-Iuan Liu:
An All-Digital Despreading Clock Generator. 16-20 - P. Stoliar, Pablo Levy, Maria Jose Sanchez, A. G. Leyva, C. A. Albornoz, Fernando Gomez-Marlasca, A. Zanini, C. Toro Salazar, Nestor Fabian Ghenzi, Marcelo J. Rozenberg:
Nonvolatile Multilevel Resistive Switching Memory Cell: A Transition Metal Oxide-Based Circuit. 21-25 - Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi:
A Subthreshold Symmetric SRAM Cell With High Read Stability. 26-30 - Tao Li, Qing Zhao, James Lam, Zhiguang Feng:
Multi-Bound-Dependent Stability Criterion for Digital Filters With Overflow Arithmetics and Time Delay. 31-35 - Hai Huyen Dam:
Variable Fractional Delay FIR Filter Design with a Bicriteria and Coefficient Relationship. 36-40 - Jinwang Liu, Dongmei Li, Licui Zheng:
The Lin-Bose Problem. 41-43 - Maurizio Porfiri:
Linear Analysis of the Vectorial Network Model. 44-48 - Jun Yang, Wei Xing Zheng:
Offset-Free Nonlinear MPC for Mismatched Disturbance Attenuation With Application to a Static Var Compensator. 49-53 - Yutaro Yamashita, Hiroyuki Torikai:
Theoretical Analysis for Efficient Design of a Piecewise Constant Spiking Neuron Model. 54-58 - Changchun Hua, Dan Liu, Xin-Ping Guan:
Necessary and Sufficient Stability Criteria for a Class of Fractional-Order Delayed Systems. 59-63
Volume 61-II, Number 2, February 2014
- Tolga Dinc, Ilker Kalyoncu, Yasar Gurbuz:
An X-Band Slow-Wave T/R Switch in 0.25-µm SiGe BiCMOS. 65-69 - Kim B. Ostman, Mikko Englund, Olli Viitala, Kari Stadius, Kimmo Koli, Jussi Ryynänen:
Characteristics of LNA Operation in Direct Delta-Sigma Receivers. 70-74 - Chen-Chien Lin, Chan-Hsiang Weng, Tzu-An Wei, Yung-Yu Lin, Tsung-Hsien Lin:
A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta-Sigma Modulator. 75-79 - Bozorgmehr Vosooghi, Li Lu, Changzhi Li:
Leakage, Area, and Headroom Tradeoffs for Scattered Relative Temperature Sensor Front-End Architectures. 80-84 - Goran Molnar, Mladen Vucic:
Bernoulli Low-Pass Filters. 85-89 - Jordi Perez-Puigdemont, Francesc Moll, Antonio Calomarde:
All-Digital Simple Clock Synthesis Through a Glitch-Free Variable-Length Ring Oscillator. 90-94 - Chun-Fu Liao, Fang-Chun Lan, Jin-Wei Jhang, Yuan-Hao Huang:
A 576-Mbit/s 64-QAM 4 × 4 MIMO Precoding Processor With Lattice Reduction. 95-99 - Karthik Subburaj, Sumeer Bhatara, Jawaharlal Tangudu, J. R. Samuel, Raghu Ganesan, Karthik Ramasubramanian:
Spur Mitigation in High-Sensitivity GNSS Receivers. 100-104 - Ashkan Ashrafi:
Optimization of the Quantized Coefficients for DDFS Utilizing Polynomial Interpolation Methods. 105-109 - Weihua Zheng, Kenli Li, Keqin Li:
A Fast Algorithm Based on SRFFT for Length N = q × 2m DFTs. 110-114 - Chuan Zhang, Keshab K. Parhi:
Latency Analysis and Architecture Design of Simplified SC Polar Decoders. 115-119 - Jangwon Park, Jongsun Park, Swarup Bhunia:
VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications. 120-124 - Siavash Bayat Sarmadi, Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee:
Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures. 125-129
Volume 61-II, Number 3, March 2014
- Ken-Fu Liang, Jau-Horng Chen, Yi-Jan Emery Chen:
A Quadratic-Interpolated LUT-Based Digital Predistortion Technique for Cellular Power Amplifiers. 133-137 - Fang Zhu, Wei Hong, Jixin Chen, Xin Jiang, Ke Wu, Pinpin Yan, Chun-Lin Han:
A Broadband Low-Power Millimeter-Wave CMOS Downconversion Mixer With Improved Linearity. 138-142 - Nicola Da Dalt:
An Analysis of Phase Noise in Realigned VCOs. 143-147 - Dennis R. Morgan:
Combined Three-State/PWM Signal Coding for Wideband High-Efficiency Class-S Amplifiers. 148-152 - Sang-Hye Chung, Young-Ju Kim, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Lee-Sup Kim:
A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth. 153-157 - Michele Bonnin, Fernando Corinto:
Influence of Noise on the Phase and Amplitude of Second-Order Oscillators. 158-162 - Chun-Chi Chen, Shih-Hao Lin, Chorng-Sii Hwang:
An Area-Efficient CMOS Time-to-Digital Converter Based on a Pulse-Shrinking Scheme. 163-167 - Antonio C. C. Telles, Saulo Finco, Jose Antenor Pomilio:
Modeling of a MOS Ultralow Voltage Astable Multivibrator for Energy Harvesting. 168-172 - Kwanyeob Chae, Saibal Mukhopadhyay:
Resilient Pipeline Under Supply Noise With Programmable Time Borrowing and Delayed Clock Gating. 173-177 - Xuelian Liu, Srikumar Raman, Ryan Clarke, Mitchell R. LeRoy, Okan Erdogan, Michael Chu, Alexey Gutin, Russell P. Kraft, John F. McDonald:
Design of High-Speed Register Files Using SiGe HBT BiCMOS Technology. 178-182 - Bishnu Prasad Das, Hidetoshi Onodera:
On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator. 183-187 - Dao-Ping Wang, Hon-Jarn Lin, Ching-Te Chuang, Wei Hwang:
Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors. 188-192 - Jisu Kim, Taehui Na, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
A Split-Path Sensing Circuit for Spin Torque Transfer MRAM. 193-197 - Jeevan K. Pant, Wu-Sheng Lu, Andreas Antoniou:
New Improved Algorithms for Compressive Sensing Based on ℓp Norm. 198-202 - Shunsuke Koshita, Masahide Abe, Masayuki Kawamata:
A Simple Ladder Realization of Maximally Flat Allpass Fractional Delay Filters. 203-207
Volume 61-II, Number 4, April 2014
- Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Ni Xu, Woogeun Rhee, Liji Wu, Chun Zhang:
A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS. 209-213 - Ekaterina Panina, Lucio Pancheri, Gian-Franco Dalla Betta, Nicola Massari, David Stoppa:
Compact CMOS Analog Counter for SPAD Pixel Arrays. 214-218 - Taner Sumesaglam:
An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS. 219-223 - Jaejin Yeo, Yongsuk Choi, Jeongjin Roh, Gunhee Han, Youngcheol Chae, Seogheon Ham:
A Current Regulator for Inverter-Based Massively Column-Parallel ΔΣ ADCs. 224-228 - Younghyun Yoon, Hyungdong Roh, Jeongjin Roh:
A True 0.4-V Delta-Sigma Modulator Using a Mixed DDA Integrator Without Clock Boosted Switches. 229-233 - Kim B. Ostman, Jani K. Jarvenhaara, Svetozar S. Broussev, Ismo Viitaniemi:
A 3.6-to-1.8-V Cascode Buck Converter With a Stacked LC Filter in 65-nm CMOS. 234-238 - Kang-Sub Kwak, Oh-Kyong Kwon:
Power-Reduction Technique Using a Single Edge-Tracking Clock for Multiphase Clock and Data Recovery Circuits. 239-243 - Weibo Li, Yoshitaka Niimi, Yuichiro Orino, Shinnosuke Hirata, Minoru Kuribayashi Kurosawa:
A Frequency Synchronization Method for a Self-Oscillating PWM Signal Generator. 244-248 - Antonino M. Sommariva:
On Brune's Tests. 249-253 - Jack Shiah, Shahriar Mirabbasi:
A 5-V 290-µW Low-Noise Chopper-Stabilized Capacitive-Sensor Readout Circuit in 0.8-µm CMOS Using a Correlated-Level-Shifting Technique. 254-258 - Adam Teman, Pascal Andreas Meinerzhagen, Robert Giterman, Alexander Fish, Andreas Burg:
Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM. 259-263 - Jianhui Wu, Jiafeng Zhu, YingCheng Xia, Na Bai:
A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers. 264-268 - Toshihiro Hori:
Novel One-Dimensional Sampling Method to Calculate Two-Dimensional Diamond-Shaped Discrete Frequency Distributions. 269-273 - JinWoo Yoo, JaeWook Shin, PooGyeon Park:
Variable Step-Size Affine Projection Sign Algorithm. 274-278 - Chamira U. S. Edussooriya, Len T. Bruton, Mehdi Ataei Naeini, Panajotis Agathoklis:
Using 1-D Variable Fractional-Delay Filters to Reduce the Computational Complexity of 3-D Broadband Multibeam Beamformers. 279-283 - Soo-Chang Pei, Chia-Chang Wen, Jian-Jiun Ding:
Conjugate Symmetric Discrete Orthogonal Transform. 284-288
Volume 61-II, Number 5, May 2014
- Heein Yoon, Yongsun Lee, Jae Joon Kim, Jaehyouk Choi:
A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core. 289-293 - Arindam Sanyal, Nan Sun:
An Energy-Efficient Low Frequency-Dependence Switching Technique for SAR ADCs. 294-298 - Y. Liang, Hao Chen, D. S. Yu:
A Practical Implementation of a Floating Memristor-Less Meminductor Emulator. 299-303 - Taeho Kim, Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Jiheon Park, Deog-Kyoon Jeong:
A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process. 304-308 - Carlos Sánchez-López, Jorge Mendoza-Lopez, Miguel Ángel Carrasco-Aguilar, Carlos Muñiz-Montero:
A Floating Analog Memristor Emulator Circuit. 309-313 - Jia Mao, Zhuo Zou, Li-Rong Zheng:
A Subgigahertz UWB Transmitter With Wireless Clock Harvesting for RF-Powered Applications. 314-318 - Joung-Wook Moon, Kwang-Chun Choi, Woo-Young Choi:
A 0.4-V, 90 ∼ 350-MHz PLL With an Active Loop-Filter Charge Pump. 319-323 - Lianxi Liu, Shijie Deng, Zhangming Zhu, Yintang Yang:
A 2.1-Channel Class-D Amplifier Exploited Coupling Virtual-Audio-Image to Enhance Stereo. 324-328 - Byoungho Kim, Jacob A. Abraham:
Dynamic Performance Characterization of Embedded Single-Ended Mixed-Signal Circuits. 329-333 - Kuo-Ken Huang, David D. Wentzloff:
A 1.2-MHz 5.8-µW Temperature-Compensated Relaxation Oscillator in 130-nm CMOS. 334-338 - Hung-Yen Tai, Cheng-Hsueh Tsai, Pao-Yang Tsai, Hung-Wei Chen, Hsin-Shu Chen:
A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS. 339-343 - Amit Ranjan Trivedi, Wen Yueh, Saibal Mukhopadhyay:
In Situ Power Gating Efficiency Learner for Fine-Grained Self-Adaptive Power Gating. 344-348 - Abdelkrim Kamel Oudjida, Nicolas Chaillet:
Radix-2r Arithmetic for Multiplication by a Constant. 349-353 - Jiangpeng Li, Kai Zhao, Jun Ma, Tong Zhang:
Realizing Unequal Error Correction for nand Flash Memory at Minimal Read Latency Overhead. 354-358 - Guanghui Wen, Guoqiang Hu, Wenwu Yu, Guanrong Chen:
Distributed H∞ Consensus of Higher Order Multiagent Systems With Switching Topologies. 359-363 - Walter J. Kozacky, Tokunbo Ogunfunmi:
Convergence Analysis of an Adaptive Algorithm With Output Power Constraints. 364-367 - Chien-Cheng Tseng, Su-Ling Lee:
On the Designs of Variable Fractional Hilbert Transformers. 368-372
Volume 61-II, Number 6, June 2014
- Zheng Gao, Ping Gui, Rick Jordanger:
An Integrated High-Voltage Low-Distortion Current-Feedback Linear Power Amplifier for Ultrasound Transmitters Using Digital Predistortion and Dynamic Current Biasing Techniques. 373-377 - David Gaied, Emad Hegazi:
Charge-Pump Folded Noise Cancelation in Fractional-N Phase-Locked Loops. 378-382 - Francisco Colodro, Antonio Torralba:
Linearity Enhancement of VCO-Based Quantizers for SD Modulators by Means of a Tracking Loop. 383-387 - Matthias Lorenz, Rudolf Ritter, Joachim Becker, Maurits Ortmanns:
A Genetic Algorithm for the Estimation of Nonidealities in Continuous-Time Sigma-Delta Modulators. 388-392 - Gitae Pyo, Jaemo Yang, Choul-Young Kim, Songcheol Hong:
K-Band Dual-Mode Receiver CMOS IC for FMCW/UWB Radar. 393-397 - Adi Xhakoni, Georges G. E. Gielen:
A 132-dB Dynamic-Range Global-Shutter Stacked Architecture for High-Performance Imagers. 398-402 - Lin He, Yuncheng Zhang, Fang Long, Fengcheng Mei, Mingyuan Yu, Fujiang Lin, Libin Yao, Xicheng Jiang:
Digital Noise-Coupling Technique for Delta-Sigma Modulators With Segmented Quantization. 403-407 - Younghoon Kim, Changsik Yoo:
A 100-kS/s 8.3-ENOB 1.7- µW Time-Domain Analog-to-Digital Converter. 408-412 - Hamed Aminzadeh, Mohammad R. Nabavi, Wouter A. Serdijn:
Low-Dropout Voltage Source: An Alternative Approach for Low-Dropout Voltage Regulators. 413-417 - Basant Kumar Mohanty, Sujit Kumar Patel:
Area-Delay-Power Efficient Carry-Select Adder. 418-422 - Zheng Yu, Zhiyi Yu, Xueqiu Yu, Ningxi Liu, Xiaoyang Zeng:
Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process. 423-427 - Sumit Jagdish Darak, A. Prasad Vinod, Edmund Ming-Kit Lai, Jacques Palicot, Honggang Zhang:
Linear-Phase VDF Design With Unabridged Bandwidth Control Over the Nyquist Band. 428-432 - Anand D. Darji, Shubham Agrawal, Ankit Oza, Vipul Sinha, Aditya Verma, S. N. Merchant, Arun N. Chandorkar:
Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform. 433-437 - Seok Kim, Eun-Young Jin, Kee-Won Kwon, Jintae Kim, Jung-Hoon Chun:
A 6.4-Gb/s Voltage-Mode Near-Ground Receiver With a One-Tap Data and Edge DFE. 438-442 - Asma Maalej, Manel Ben-Romdhane, Chiheb Rebai, Adel Ghazel, Patricia Desgreys, Patrick Loumeau:
Toward Time-Quantized Pseudorandom Sampling for Green Communication. 443-447 - Haiyan Shu, Rongshan Yu, Wenyu Jiang, Wenxian Yang:
Efficient Implementation of k-Nearest Neighbor Classifier Using Vote Count Circuit. 448-452 - Xi-Ming Sun, Di Wu, Changyun Wen, Wei Wang:
A Novel Stability Analysis for Networked Predictive Control Systems. 453-457
Volume 61-II, Number 7, July 2014
- Arindam Sanyal, Peijun Wang, Nan Sun:
A Thermometer-Like Mismatch Shaping Technique With Minimum Element Transition Activity for Multibit ΔΣ DACs. 461-465 - Annachiara Spagnolo, Bob Verbruggen, Piet Wambacq, Stefano D'Amico:
A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS. 466-470 - Yun Yin, Baoyong Chi, Zhaokang Xia, Zhihua Wang:
A Reconfigurable Dual-Mode CMOS Power Amplifier With Integrated T/R Switch for 0.1-1.5-GHz Multistandard Applications. 471-475 - Lei Sun, Chi-Tung Ko, Kong-Pang Pun:
Optimizing the Stage Resolution in Pipelined SAR ADCs for High-Speed High-Resolution Applications. 476-480 - Hye-Jung Kwon, Jae-Seung Lee, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current. 481-485 - Jing Li, Shuangyi Wu, Yang Liu, Ning Ning, Qi Yu:
A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs. 486-490 - Zdenek Biolek, Dalibor Biolek:
How Can the Hysteresis Loop of the Ideal Memristor Be Pinched? 491-495 - Jerrin Pathrose, Lei Zou, Kevin T. C. Chai, Minkyu Je, Yong Ping Xu:
Temperature Sensor Front End in SOI CMOS Operating up to 250°C. 496-500 - Golsa Moayeri Pour, Mohammad K. Benyhesan, Walter D. Leon-Salas:
Energy Harvesting Using Substrate Photodiodes. 501-505 - Alexander Edward, José Silva-Martínez:
General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators. 506-510 - Sang Yoon Park, Pramod Kumar Meher:
Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter. 511-515 - Quan Xu, Thomas M. Chen, Yupeng Hu, Pu Gong:
Write Pattern Format Algorithm for Reliable NAND-Based SSDs. 516-520 - Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul:
Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder. 521-525 - Davide De Caro, Mariangela Genovese, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo:
Accurate Fixed-Point Logarithmic Converter. 526-530 - Chunguo Li, Fan Sun, John M. Cioffi, Luxi Yang:
Energy Efficient MIMO Relay Transmissions via Joint Power Allocations. 531-535 - Sheng Zhang, Jiashu Zhang:
Set-Membership NLMS Algorithm With Robust Error Bound. 536-540 - Lan Gao, Xiaofeng Liao, Huaqing Li:
Pinning Controllability Analysis of Complex Networks With a Distributed Event-Triggered Mechanism. 541-545
Volume 61-II, Number 8, August 2014
- Mincheol Seo, Hwiseob Lee, Jehyeon Gu, Hyungchul Kim, Junghyun Ham, Wooyeol Choi, Yanghun Yun, Kenneth K. O, Youngoo Yang:
High-Efficiency Power Amplifier Using an Active Second-Harmonic Injection Technique Under Optimized Third-Harmonic Termination. 549-553 - Yong-Hwan Moon, In-Seok Kong, Young-Soo Ryu, Jin-Ku Kang:
A 2.2-mW 20-135-MHz False-Lock-Free DLL for Display Interface in 0.15-µm CMOS. 554-558 - Kuo-Hsing Cheng, Cheng-Liang Hung, Cihun-Siyong Alex Gong, Jen-Chieh Liu, Bo-Qian Jiang, Shi-Yang Sun:
A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes. 559-563 - Chao Chen, Jianhui Wu, Dan Huang, Longxing Shi:
A Low-Power 2.4-GHz Receiver Front End With a Lateral Current-Reusing Technique. 564-568 - Reza Hashemian:
Fixator-Norator Pairs Versus Direct Analytical Tools in Performing Analog Circuit Designs. 569-573 - Fermin Esparza-Alfaro, Salvatore Pennisi, Gaetano Palumbo, Antonio J. López-Martín:
Low-Power Class-AB CMOS Voltage Feedback Current Operational Amplifier With Tunable Gain and Bandwidth. 574-578 - Fan Xie, Bo Zhang, Ru Yang, Dong Yuan Qiu:
Quantifying the Complexity of DC-DC Switching Converters by Joint Entropy. 579-583 - Mohammad Taherzadeh-Sani, Reza Lotfi, Frederic Nabki:
A 10-bit 110 kS/s 1.16 µW SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications. 584-588 - Hesham Omran, Muhammad Arsalan, Khaled N. Salama:
7.9 pJ/Step Energy-Efficient Multi-Slope 13-bit Capacitance-to-Digital Converter. 589-593