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Arnaud Poittevin
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2020 – today
- 2022
- [c5]Arnaud Poittevin, Ian O'Connor, Cédric Marchand, Alberto Bosio, Cristell Maneux, Chhandak Mukherjee, Guilhem Larrieu, Abhishek Kumar:
A Logic Cell Design and routing Methodology Specific to VNWFET. NEWCAS 2022: 460-464 - [c4]Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng
, François Marc, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu, Arnaud Poittevin, Ian O'Connor, Oskar Baumgartner, David Pirker:
Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors. VLSI-SoC 2022: 1-2 - 2021
- [c3]Alberto Bosio, Mayeul Cantan
, Cédric Marchand
, Ian O'Connor, Petr Fiser, Arnaud Poittevin, Marcello Traiola
:
Emerging Technologies: Challenges and Opportunities for Logic Synthesis. DDECS 2021: 93-98 - 2020
- [c2]Chhandak Mukherjee, Marina Deng
, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor
, Sébastien Le Beux, Cédric Marchand
, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu:
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. VLSI-SOC 2020: 76-81 - [c1]Arnaud Poittevin, Chhandak Mukherjee, Ian O'Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng
, Sébastien Le Beux, François Marc, Aurélie Lecestre, Cédric Marchand
, Abhishek Kumar:
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. VLSI-SoC (Selected Papers) 2020: 301-321 - [i1]C. Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu:
3D logic cells design and results based on Vertical NWFET technology including tied compact model. CoRR abs/2005.14039 (2020)
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