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ORCIDGanapathy Parthasarathy
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2020 – today
- 2024
[i1]Bhuvnesh Kumar, Saurav Nanda, Ganapathy Parthasarathy, Pawan Patil, Austin Tsai, Parivesh Choudhary:
HDL-GPT: High-Quality HDL is All You Need. CoRR abs/2407.18423 (2024)- 2023
- [c19]Bhuvnesh Kumar, Ganapathy Parthasarathy
, Saurav Nanda, Sridhar Rajakumar:
Optimizing Constrained Random Verification with ML and Bayesian Estimation. MLCAD 2023: 1-6 - 2022
- [c18]Ganapathy Parthasarathy, Aabid Rushdi, Parivesh Choudhary, Saurav Nanda, Malan Evans, Hansika Gunasekara, Sridhar Rajakumar:
RTL Regression Test Selection using Machine Learning. ASP-DAC 2022: 281-287 - [c17]Ganapathy Parthasarathy, Bhuvnesh Kumar, Saurav Nanda, Parivesh Choudhary, Sridhar Rajakumar:
Optimizing ML Classification Models for Constrained EDA Resource Budgets. ICCD 2022: 223-230
2010 – 2019
- 2019
- [c16]Saurav Nanda, Ganapathy Parthasarathy, Parivesh Choudhary, Arun Venkatachar:
Resource Aware Scheduling for EDA Regression Jobs. Euro-Par Workshops 2019: 639-651 - 2017
- [c15]Arun Venkatachar, S. Rajakumar, M. Chapman, Sajeewan Basuru, Ganapathy Parthasarathy, C.-C. Lin, A. Hegde, T. Li:
Test Knowledge Data Base. VLSI-DAT 2017: 1-4
2000 – 2009
- 2005
- [c14]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer:
Structural search for RTL with predicate learning. DAC 2005: 451-456 - [c13]Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng:
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver. DATE 2005: 666-671 - [c12]Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen:
An Efficient Sequential SAT Solver With Improved Search Strategies. DATE 2005: 1102-1107 - [c11]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer:
RTL SAT simplification by Boolean and interval arithmetic reasoning. ICCAD 2005: 297-302 - 2004
- [j2]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang:
Safety Property Verification Using Sequential SAT and Bounded Model Checking. IEEE Des. Test Comput. 21(2): 132-143 (2004) - [c10]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang:
Efficient reachability checking using sequential SAT. ASP-DAC 2004: 418-423 - [c9]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang:
An efficient finite-domain constraint solver for circuits. DAC 2004: 212-217 - 2003
- [c8]Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang:
A comparison of BDDs, BMC, and sequential SAT for model checking. HLDVT 2003: 157-162 - [c7]Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng:
SATORI - A Fast Sequential SAT Engine for Circuits. ICCAD 2003: 320-325 - 2002
- [j1]Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska:
Efficient circuit clustering for area and power reduction in FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4): 643-663 (2002) - [c6]Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir:
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. ITC 2002: 203-212 - 2001
- [c5]Ganapathy Parthasarathy, Chung-Yang Huang, Kwang-Ting Cheng:
An analysis of ATPG and SAT algorithms for formal verification. HLDVT 2001: 177-182 - [c4]Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska:
Interconnect Resource-Aware Placement for Hierarchical FPGAs. ICCAD 2001: 132-136 - [c3]Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee, Amit Singh:
Interconnect complexity-aware FPGA placement using Rent's rule. SLIP 2001: 115-121
1990 – 1999
- 1999
- [c2]Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss:
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. VLSI Design 1999: 434-439 - 1998
- [c1]Ganapathy Parthasarathy, Michael L. Bushnell:
Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. VTS 1998: 210-217
Coauthor Index
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