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ORCIDITC 2002: Baltimore, MD, USA
- Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002. IEEE Computer Society 2002, ISBN 0-7803-7543-2
Homegrown versus Commercial Solutions for Low-Cost Text
- Bozena Kaminska:
Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines. 23 - Bill Bottoms:
Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines. 24 - Gregory S. Spirakis:
Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines. 25 - Dale E. Hoffman:
Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines. 26
Testing the Tester
- Rochit Rajsuman:
Testing The Tester. 27 - Alfred L. Crouch:
Testing the Tester: What Broke? Where? When? Why? 28 - John C. Johnson:
Testing the Tester: Specification and Validation Approaches. 29 - Rochit Rajsuman:
Testing The Tester. 30
Plenary
- Alex d'Arbeloff:
Managing in the ATE Business - Postcards from the Past, Lessons for the Future. 12 - Peter C. Maxwell:
The Heisenberg Uncertainty of Test. 13
Memory Testing
- Jean-Michel Portal, L. Forli, Hassen Aziza, Didier Née:
An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell. 31-36 - Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu:
Diagonal Test and Diagnostic Schemes for Flash Memorie. 37-46 - A. T. Sivaram, Daniel Fan, A. Yiin:
Efficient Embedded Memory Testing with APG. 47-54
Advances in Soc Testing
- Bart Vermeulen, Tom Waayers, Sjaak Bakker:
EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. 55-63 - Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing. 64-73 - Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan:
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. 74-82
Defect-Oriented Test
- Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita:
On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. 83-89 - Jaume Segura
, Ali Keshavarzi, Jerry M. Soden, Charles F. Hawkins:
Parametric Failures in CMOS ICs - A Defect-Based Analysis. 90-99 - Cecilia Metra, Stefano Di Francescantonio, T. M. Mak:
Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. 100-109
High-Performance Timing Measurements
- Hideo Okawara:
Frequency/Phase Movement Analy i by Orthogonal Demodulation. 110-119 - Mani Soma, Welela Haileselassie, Jessica Yan, Rajesh Raina:
A Wavelet-Based Timing Parameter Extraction Method. 120-128 - Sassan Tabatabaei, André Ivanov:
An Embedded Core for Sub-Picosecond Timing Measurements. 129-137
Test Data Reduction
- M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor:
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume. 138-147 - Vishal Jain, John A. Waicukauski:
Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique. 148-153 - Erik H. Volkerink, Ajay Khoche, Subhasish Mitra:
Packet-Based Input Test Data Compression Techniques. 154-163
Memory DFT, Bist and Repair
- Osamu Hirabayashi, Azuma Suzuki, Tomoaki Yabe, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Akihito Tohata, Nobuaki Otsuka:
DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs. 164-169 - Shigeki Tomishima, Hiroaki Tanizaki, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka, T. Tada, Kenji Gamo:
A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test. 170-177 - Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steven F. Oakland, Michael Ouellette, Donald L. Wheater:
On-Chip Repair and an ATE Independent Fusing Methodology. 178-186 - Jayasanker Jayabalan, Juraj Povazanec:
Integration of SRAM Redundancy into Production Test. 187-193
Design Validation - Novel ATPG Applications
- Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab:
Verifying Properties Using Sequential ATPG. 194-202 - Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir:
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. 203-212 - Jayanta Bhadra, Narayanan Krishnamurthy:
Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits. 213-222 - Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri:
Design Rewiring Using ATPG. 223-232
Novel Techniques for Diagnostics
- Ronald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels:
Fault Tuples in Diagnosis of Deep-Submicron Circuits. 233-241 - Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura:
A Persistent Diagnostic Technique for Unstable Defects. 242-249 - David B. Lavo, Ismed Hartanto, Tracy Larrabee:
Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis. 250-259 - Camelia Hora, Rene Segers, Stefan Eichenberger, Maurice Lousberg:
An Effective Diagnosis Method to Support Yield Improvement. 260-269
Connecting Disconnects
- Tom Austin, Charisma Canlas, Brady Morgan, Jorge L. Rodriguez:
Across the Great Divide: Examination of Simulation Data with Actual Silicon Waveforms Improves Device Characterization and Production Test Development. 270-279 - A. T. Sivaram, William Fritzsche, Toshitaka Koshi, Nam Lai:
DUT Capture Using Simultaneous Logic Acquisition. 280-289 - Gregory A. Maston:
Considerations for STIL Data Application. 290-296 - Guy Peterson:
Verification of Device Interface Hardware Interconnections Prior to the Start of Testing. 297-300
Test Data Compression
- Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian:
Embedded Deterministic Test for Low-Cost Manufacturing Test. 301-310 - Subhasish Mitra, Kee Sup Kim:
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction. 311-320 - C. V. Krishna, Nur A. Touba:
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression. 321-330 - Francis G. Wolff, Christos A. Papachristou:
Multiscan-Based Test Compression and Hardware Decompression Using LZ77. 331-339
Lecture Series - Embedded IP for Soc Infrastructure
- Yervant Zorian:
Embedded Memory Test and Repair: Infrastructure IP for SOC Yield. 340-349 - Mark Craig, Alvin Jee, Prashant Maniar:
An Integrated Approach to Yield Loss Characterization. 350-356 - Eric Dupont, Michael Nicolaidis:
Robustness IPs for Reliability and Security of SoCs. 357-364
Chip-Level Crosstalk Identification and Testing
- Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer:
XIDEN: Crosstalk Target Identification Framework. 365-374 - Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal:
Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. 375-383 - Bipul Chandra Paul, Kaushik Roy:
Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis. 384-390
Advances in Fault Simulation and Test Generation
- A. V. S. S. Prasad, Vishwani D. Agrawal, Madhusudan V. Atre:
A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets. 391-397 - Li-C. Wang, Magdy S. Abadir, Juhong Zhu:
On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults. 398-406 - Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams:
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. 407-416
Adventures in Interfacing
- David Gessel, Alexander H. Slcoum, Alexander D. Sprunt, Scott Ziegenhagen:
Realistic Spring Probe Testing Methods and Results. 417-423 - Kenichi Kataoka, Toshihiro Itoh, Katsuya Okumura, Tadatomo Suga:
Low-Contact-Force Probing on Copper Electrodes. 424-429 - Wolfram Humann:
Compensation of Transmission Line Loss for Gbit/s Test on ATEs. 430-437
DFT Testers
- John S. Davis, David C. Keezer:
Multi-Purpose Digital Test Core Utilizing Programmable Logic. 438-445 - Stephen K. Sunter, Benoit Nadeau-Dostie:
Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost. 446-455 - Mike Mayberry, John Johnson, Navid Shahriari, Mike Tripp:
Realizing the Benefits of Structural Test for Intel Microprocessors. 456-463
Production Test Automation
- David Turner, David Abercrombie, James McNames, W. Robert Daasch, Robert Madge:
Isolating and Removing Sources of Variation in Test Data. 464-471 - Rajneesh Mahajan, Ramesh Govindarajulu, James R. Armstrong, F. Gail Gray:
A Multi-Language Goal-Tree Based Functional Test Planning System. 472-481 - David Williams, Anthony P. Ambler:
System Manufacturing Test Cost Model. 482-490
Soft and Hard Failure Analysis and On-Line Testing
- Yi Zhao, Li Chen, Sujit Dey:
On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips. 491-499 - Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
Static Analysis of SEU Effects on Software Applications. 500-508 - Sreejit Chakravarty, Ankur Jain, Nandakumar Radhakrishnan, Eric W. Savage, Sujit T. Zachariah:
Experimental Evaluation of Scan Tests for Bridges. 509-518
Soc Benchmarks
- Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty:
A Set of Benchmarks fo Modular Testing of SOCs. 519-528 - Sandeep Kumar Goel, Erik Jan Marinissen:
Effective and Efficient Test Architecture Design for SOCs. 529-538 - Sandeep Koranne, Vikram Iyengar:
On the Use of k-tuples for SoC Test Schedule Representation. 539-548
Appliaction Series - High-Speed Test Interfaces
- Todd Sargent:
Physical Principles of Interface Design. 549-554 - Thomas P. Warwick:
What a Device Interface Board Really Costs: An Evaluation of Technical Considerations for Testing Products Operating in the Gigabit Region. 555-564 - David E. McFeely:
The Process and Challenges of a High-Speed DUT Board Project. 565-573
Test and Debug of Microprocessors
- Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina:
Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. 574-583 - Timothe Litt:
Support for Debugging in the Alpha 21364 Microprocessor. 584-589 - Praveen Parvathala, Kaila Maneparambil, William Lindsay:
FRITS - A Microprocessor Functional BIST Method. 590-598
FPGA Testing
- Shahin Toutounchi, Andrew Lai:
FPGA Test and Coverage. 599-607 - Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey:
Fault Grading FPGA Interconnect Test Configurations. 608-617 - Charles E. Stroud, Jeremy Nall, Matthew Lashinsky, Miron Abramovici:
BIST-Based Diagnosis of FPGA Interconnect. 618-627
Lecture Series-Silicon Debug
- Hari Balachandran, Kenneth M. Butler, Neil Simpson:
Facilitating Rapid First Silicon Debug. 628-637 - Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel:
Core-Based Scan Architecture for Silicon Debug. 638-647 - Xinli Gu, Weili Wang, Kevin Li, Heon C. Kim, Sung Soo Chung:
Re-Using DFT Logic for Functional and Silicon Debugging Test. 648-656 - Don Douglas Josephson:
The Manic Depression of Microprocessor Debug. 657-663 - Carol Pyron, Rekha Bangalore, Dawit Belete, Jason Goertz, Ashutosh Razdan, Denise Younger:
Silicon Symptoms to Solutions: Applying Design for Debug Techniques. 664-672
Data Analysis and Yield Model Validation
- Robert Madge, B. H. Goh, V. Rajagopalan, C. Macchietto, W. Robert Daasch, Chris Schuermyer, C. Taylor, David Turner:
Screening MinVDD Outliers Using Feed-Forward Voltage Testing. 673-682 - Minh Quach, Tuan Pham, Tim Figal, Bob Kopitzke, Pete O'Neill:
Wafer-Level Defect-Based Testing Using Enhanced Voltage Stress and Statistical Test Data Evaluation. 683-692 - Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh:
Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model. 693-699
Jitter Testing in Multi-Gigahertz Digital Systems
- Yi Cai, S. A. Werner, G. J. Zhang, M. J. Olsen, Robert D. Brink:
Jitter Testing for Multi-Gigabit Backplane SerDes - Techniques to Decompose and Combine Various Types of Jitter. 700-709 - Mike P. Li, Jan B. Wilstrup:
On the Accuracy of Jitter Separation from Bit Error Rate Function. 710-716 - Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Hirobumi Musha, Louis Malarsie:
A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter. 717-725
Efficient Approaches to Soc Testing
- Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar:
A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors. 726-735 - Sungbae Hwang, Jacob A. Abraham:
Optimal BIST Using an Embedded Microprocessor. 736-745
1149.1 Verification and Validation
- Dave Stang, Ramaswami Dandapani:
An Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-Compliance Improvements. 746-754 - Michael Cogswell, Shazia Mardhani, Kevin Melocco, Hina Arora:
A Structured Graphical Tool for Analyzing Boundary Scan Violations. 755-762 - Adam Kristof:
Improved Digital I/O Ports Enhance Testability of Interconnections. 763-772 - Sezer Gören, F. Joel Ferguson:
Testing Finite State Machines Based on a Structural Coverage Metric . 773-780
Scan Stitching
- David Berthelot, Samit Chaudhuri, Hamid Savoj:
An Efficient Linear Time Algorithm for Scan Chain Optimization and Repartitioning. 781-787 - Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur:
Integrating DFT in the Physical Synthesis Flow. 788-795 - Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Power Driven Chaining of Flip-Flops in Scan Architectures. 796-803 - Frank te Beest, Ad M. G. Peeters, Marc Verra, Kees van Berkel, Hans G. Kerkhoff:
Automatic Scan Insertion and Test Generation for Asynchronous Circuits. 804-813
DFT for Manufacturing Problems
- Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras:
RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. 814-823 - Zhigang Jiang, Sandeep K. Gupta:
An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes. 824-833 - Seongmoon Wang:
Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST. 834-843 - Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Scan Power Reduction Through Test Data Transition Frequency Analysis. 844-850
Mixed-Signal Test Techniques
- Carsten Wegener, Michael Peter Kennedy:
Implementation of Model-Based Testing for Medium to High-Resolution Nyquist-Rate ADCs. 851-860 - M. Stancic, Liquan Fang, M. H. H. Weusthof, R. M. W. Tijink, Hans G. Kerkhoff:
A New Test Generation Approach for Embedded Analogue Cores in SoC. 861-869 - Gunter Krampl, Marco Rona, Hermann Tauber:
Test Setup Simulation - A High-Performance VHDL-Based Virtual Test Solution Meeting Industrial Requirements. 870-878 - Maurizio Gavardoni:
Use of Pipeline Converters for ATE Applications. 879-884
Go-Fast ATE!
- Ahmed Rashid Syed:
R4X/D4X - Formatters for Flexible Test System Architecture. 885-893 - Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto:
CMOS Circuit Technology for Precise GHz Timing Generator. 894-902 - Masashi Shimanouchi:
New Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device Testing. 903-912 - Jean-Pascal Mallet:
High Current DPS Architecture for Sort Test Challenge. 913-922
System Test Design, Bist and System Verification
- Tapan J. Chakraborty, Chen-Huan Chiang:
A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur. 923-929 - Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei:
Efficient Design of System Test: A Layered Architecture. 930-939 - Liviu Miclea, Szilárd Enyedi, Alfredo Benso:
Itelligent Agents and BIST/BISR - Working Together in Distributed Systems. 940-946
Advances in IDDX
- Bartomeu Alorda, M. Rosales, Jerry M. Soden, Charles F. Hawkins, Jaume Segura:
Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs. 947-953 - David I. Bergman, Hans Engler:
Improved IDDQ Testing with Empirical Linear Prediction. 954-963 - Bram Kruseman, Stefan van den Oetelaar, Josep Rius:
Comparison of IDDQ Testing and Very-Low Voltage Testing. 964-973
Delay-Test
- Manish Sharma, Janak H. Patel:
Finding a Small Set of Longest Testable Paths that Cover Every Gate. 974-982