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2020 – today
- 2024
[j8]Shanshan Xie
, Can Ni, Aseem Sayal, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni:
eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters. IEEE J. Solid State Circuits 59(6): 1950-1961 (2024)- 2022
- [j7]Harshit Gujral, Abhinav Sharma, Pulkit Jain, Shriya Juneja, Sangeeta Mittal:
Design and Implementation of a Quantitative Network Health Monitoring and Recovery System. Wirel. Pers. Commun. 125(1): 367-397 (2022) - [c10]Shanshan Xie, Can Ni, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni:
Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs. VLSI Technology and Circuits 2022: 112-113 - 2021
- [j6]Som Sekhar Bhattacharyya, Sumi Jha, Shubham Khandelwal, Pulkit Jain, Anshul Ekka:
Development of a Model for Review Sharing in the Context of Mobile Phone Purchase Amongst Indian Millennials. Int. J. Asian Bus. Inf. Manag. 12(2): 137-156 (2021) - [c9]Shanshan Xie, Can Ni, Aseem Sayal, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni:
16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing. ISSCC 2021: 248-250 - [i1]Manuel Ntumba, Saurabh Gore, Pulkit Jain, Jean-Baptiste Awanyo:
GNC Analysis and Robotic Systems Configuration of Collision-free Earth Observation Satellites (CfEOS) Constellations. CoRR abs/2110.11387 (2021)
2010 – 2019
- 2019
- [c8]Pulkit Jain, Umut Arslan, Meenakshi Sekhar, Blake C. Lin, Liqiong Wei, Tanaya Sahu, Juan Alzate-vinasco, Ajay Vangapaty, Mesut Meterelliyoz, Nathan Strutt, Albert B. Chen, Patrick Hentges, Pedro A. Quintero, Chris Connor, Oleg Golonzka, Kevin Fischer, Fatih Hamzaoglu:
A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V. ISSCC 2019: 212-214 - [c7]Liqiong Wei, Juan G. Alzate, Umut Arslan, Justin Brockman, Nilanjan Das, Kevin Fischer, Tahir Ghani, Oleg Golonzka, Patrick Hentges, Rawshan Jahan, Pulkit Jain, Blake C. Lin, Mesut Meterelliyoz, Jim O'Donnell, Conor Puls, Pedro A. Quintero, Tanaya Sahu, Meenakshi Sekhar, Ajay Vangapaty, Chris Wiegand, Fatih Hamzaoglu:
A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique. ISSCC 2019: 214-216 - 2015
- [j5]Xiaofei Wang, Qianying Tang, Pulkit Jain, Dong Jiao, Chris H. Kim:
The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 280-291 (2015) - 2014
- [j4]Xiaofei Wang, John Keane, Tony Tae-Hyoung Kim, Pulkit Jain, Qianying Tang, Chris H. Kim:
Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design. IEEE Micro 34(6): 74-85 (2014) - 2012
- [j3]Ki Chul Chun, Pulkit Jain, Tae-Ho Kim, Chris H. Kim:
A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches. IEEE J. Solid State Circuits 47(2): 547-559 (2012) - [j2]Ki Chul Chun, Wei Zhang, Pulkit Jain, Chris H. Kim:
A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor. IEEE J. Solid State Circuits 47(10): 2517-2526 (2012) - [c6]Pulkit Jain, John Keane, Chris H. Kim:
An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs. ESSDERC 2012: 262-265 - 2011
- [j1]Ki Chul Chun, Pulkit Jain, Jung-Hwa Lee, Chris H. Kim:
A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches. IEEE J. Solid State Circuits 46(6): 1495-1505 (2011) - [c5]Ki Chul Chun, Wei Zhang, Pulkit Jain, Chris H. Kim:
A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies. ISSCC 2011: 506-507 - 2010
- [c4]Ki Chul Chun, Pulkit Jain, Chris H. Kim:
Logic-compatible embedded DRAM design for memory intensive low power systems. ISCAS 2010: 277-280
2000 – 2009
- 2009
- [c3]Ki Chul Chun, Pulkit Jain, Chris H. Kim:
A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM. ISLPED 2009: 119-120 - 2008
- [c2]Dong Jiao, Jie Gu, Pulkit Jain, Chris H. Kim:
Enhancing beneficial jitter using phase-shifted clock distribution. ISLPED 2008: 21-26 - [c1]Pulkit Jain, Tony Tae-Hyoung Kim, John Keane, Chris H. Kim:
A multi-story power delivery technique for 3D integrated circuits. ISLPED 2008: 57-62
Coauthor Index
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