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ORCIDISSCC 2011: San Francisco, CA, USA
- IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011. IEEE 2011, ISBN 978-1-61284-303-2
Paper Sessions
Plenary Session
- Stephen Oesterle, Paul Gerrish, Peng Cong:
New interfaces to the body through implantable-system integration. 9-14 - Jo De Boeck:
Game-changing opportunities for wireless personal healthcare and lifestyle. 15-21 - Oh-Hyun Kwon:
Eco-friendly semiconductor technologies for healthy living. 22-28 - Jan M. Rabaey, Hugo De Man, Mark Horowitz, Takayasu Sakurai, Jack Sun, Dan Dobberpuhl, Kiyoo Itoh, Philippe Magarshack, Asad A. Abidi, Hermann Eul:
Beyond the horizon: The next 10x reduction in power - Challenges and solutions. 31
Technologies for Health
- Joonsung Bae, Kiseok Song, Hyungwoo Lee, Hyunwoo Cho, Long Yan, Hoi-Jun Yoo:
A 0.24nJ/b wireless body-area-network transceiver with scalable double-FSK modulation. 34-36 - Seulki Lee, Long Yan, Taehwan Roh, Sunjoo Hong, Hoi-Jun Yoo:
A 75μW real-time scalable network controller and a 25μW ExG sensor IC for compact sleep-monitoring applications. 36-38 - Yu-Te Liao
, Huanfen Yao, Babak A. Parviz, Brian P. Otis:
A 3μW wirelessly powered CMOS glucose sensor for an active contact lens. 38-40 - Domenico Zito, Domenico Pepe, Martina Mincica, Fabio Zito:
A 90nm CMOS SoC UWB pulse radar for respiratory rate monitoring. 40-41 - Franz Schuster, Hadley Videlier, Antoine Dupret, Dominique Coquillat, Maciej Sakowicz, Jean-Pierre Rostaing, Michaël Tchagaspanian, Benoît Giffard, Wojciech Knap:
A broadband THz imager in a low-cost CMOS technology. 42-43 - Shuenn-Yuh Lee, Yu-Cheng Su, Ming-Chun Liang, Jia-Hua Hong, Cheng-Han Hsieh, Chung-Min Yang, You-Yin Chen, Hsin-Yi Lai, Jou-Wei Lin, Qiang Fang:
A programmable implantable micro-stimulator SoC with wireless telemetry: Application in closed-loop endocardial stimulation for cardiac pacemaker. 44-45 - Yoonmyung Lee, Bharan Giridhar, Zhiyoong Foo, Dennis Sylvester, David T. Blaauw:
A 660pW multi-stage temperature-compensated timer for ultra-low-power wireless sensor node synchronization. 46-48 - David Ruffieux, Matteo Contaldo, Jacques Haesler, Steve Lecomte:
A low-power fully integrated RF locked loop for Miniature Atomic Clock. 48-50
RF Techniques
- Robert Bogdan Staszewski, Khurram Waheed, Sudheer K. Vemulapalli, Fikret Dulger, John L. Wallberg, Chih-Ming Hung, Oren E. Eliezer:
Spur-free all-digital PLL in 65nm for mobile phones. 52-54 - Nenad Pavlovic, Jos Bergervoet:
A 5.3GHz digital-to-time-converter-based fractional-N all-digital PLL. 54-56 - Chang-Tsung Fu, Hasnain Lakdawala, Stewart S. Taylor, Krishnamurthy Soumyanath:
A 2.5GHz 32nm 0.35mm2 3.5dB NF -5dBm P1dB fully differential CMOS push-pull LNA with integrated 34dBm T/R switch and ESD protection. 56-58 - David A. Calvillo-Cortes, Mustafa Acar, Mark P. van der Heijden, Melina Apostolidou, Leo C. N. de Vreede, Domine Leenaerts, Jan Sonsky:
A 65nm CMOS pulse-width-controlled driver with 8Vpp output voltage for switch-mode RF PAs up to 3.6GHz. 58-60 - Ahmad Mirzaei, Hooman Darabi, David Murphy:
A low-power process-scalable superheterodyne receiver with integrated high-Q filters. 60-62 - Jonathan Borremans, Gunjan Mandal, Vito Giannini, Tomohiro Sano, Mark Ingels, Bob Verbruggen, Jan Craninckx:
A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers. 62-64 - Michiel C. M. Soer, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet:
A 1.0-to-4.0GHz 65nm CMOS four-element beamforming receiver using a switched-capacitor vector modulator with approximate sine weighting via charge redistribution. 64-66 - Aslam A. Rafi, Alessandro Piovaccari, Peter J. Vancorenland, Tyson Tuttle:
A harmonic rejection mixer robust to RF device mismatches. 66-68
Enterprise Processors & Components
- James D. Warnock, Y. Chan, William V. Huott, Sean M. Carey, Michael F. Fee, Huajun Wen, Mary Jo Saccamango, Frank Malgioglio, Patrick J. Meaney, Donald W. Plass, Yuen H. Chan, Mark D. Mayo, Guenter Mayer, Leon J. Sigal, David L. Rude, Robert M. Averill III, Michael H. Wood, Thomas Strach, Howard H. Smith, Brian W. Curran, Eric M. Schwarz, Lee Eisen, Doug Malone, Steve Weitzel, Pak-kin Mak, Thomas J. McPherson, Charles F. Webb:
A 5.2GHz microprocessor chip for the IBM zEnterprise™ system. 70-72 - Antonio Pelella, Yuen H. Chan, Bargav Balakrishnan, Pradip Patel, Daniel Rodko, Richard E. Serton:
Dynamic hit logic with embedded 8Kb SRAM in 45nm SOI for the zEnterprise™ processor. 72-73 - Shankar Sawant, Utpal Desai, Gururaj Shamanna, Lokesh Sharma, Mandar Ranade, Anil Agarwal, Sampath Dakshinamurthy, Rajagopal Narayanan:
A 32nm Westmere-EX Xeon® enterprise processor. 74-75 - Weiwu Hu, Ru Wang, Yunji Chen, Bao-Xia Fan, Shi-Qiang Zhong, Xiang Gao, Zichu Qi, Xu Yang:
Godson-3B: A 1GHz 40W 8-core 128GFLOPS processor in 65nm CMOS. 76-78 - Tim C. Fischer, Srikanth Arekapudi, Eric Busta, Carl Dietz, Michael Golden, Scott Hilker, Aaron Horiuchi, Kevin A. Hurd, Dave Johnson, Hugh McIntyre, Samuel Naffziger, James Vinh, Jonathan White, Kathryn Wilcox:
Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU. 78-80 - Michael Golden, Srikanth Arekapudi, James Vinh:
40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86-64 core. 80-82 - Shenggao Li, Ashwin Krishnakumar, Edward Helder, Roan Nicholson, Vivian Jia:
Clock generation for a 32nm server processor with scalable cores. 82-83 - Reid J. Riedlinger, Rohit Bhatia, Larry Biro, William J. Bowhill, Eric S. Fetzer, Paul E. Gronowski, Tom Grutkowski:
A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers. 84-86
PLLs
- Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power. 88-90 - Che-Fu Liang, Keng-Jan Hsiao:
An injection-locked ring PLL with self-aligned injection window. 90-92 - Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu:
A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration. 92-94 - Dong-Woo Jee, Yunjae Suh, Hong-June Park, Jae-Yoon Sim:
A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering. 94-96 - Hyung-Jin Lee, Alexandra M. Kern, Sami Hyvonen, Ian A. Young:
A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS. 96-97 - Akihide Sai, Takafumi Yamaji, Tetsuro Itakura:
A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop. 98-100 - Koji Takinami, Richard Strandberg, Paul C. P. Liang, Gregoìre Le Grand de Mercey, Tony Wong, Mahnaz Hassibi:
A rotary-traveling-wave-oscillator-based all-digital PLL with a 32-phase embedded phase-to-digital converter in 65nm CMOS. 100-102
Sensors & Energy Harvesting
- Luciano Prandi, Carlo Caminada, Luca Coronato, Gabriele Cazzaniga, Fabio Biganzoli, Riccardo Antonello, Roberto Oboe:
A low-power 3-axis digital-output MEMS gyroscope with single drive and multiplexed angular rate readout. 104-106 - Jianfeng Wu, Youngcheol Chae, Caspar P. L. van Vroonhoven, Kofi A. A. Makinwa:
A 50mW CMOS wind sensor with ±4% speed and ±2° direction error. 106-108 - Matthias Kuhl, Pascal Gieschke, Daniel Rossbach, Sascha Alexander Hilzensauer, Patrick Ruther, Oliver Paul, Yiannos Manoli:
A telemetric stress-mapping CMOS chip with 24 FET-based stress sensors for smart orthodontic brackets. 108-110 - Rong Wu, Johan H. Huijsing, Kofi A. A. Makinwa:
A 21b ±40mV range read-out IC for bridge transducers. 110-112 - Frédéric Rothan, Hélène Lhermet, Brice Zongo, Cyril Condemine, Henri Sibuet, Patrick Mas, Miguel Debarnot:
A ±1.5% nonlinearity 0.1-to-100A shunt current sensor based on a 6kV isolated micro-transformer for electrical vehicles and home automation. 112-114 - Bart Dierickx, Benoit Dupont, Arnaud Defernez, Nayera Ahmed:
Indirect X-ray photon-counting image sensor with 27T pixel and 15e-rms accurate threshold. 114-116 - Suat U. Ay:
A 1.32pW/frame•pixel 1.2V CMOS energy-harvesting and imaging (EHI) APS imager. 116-118 - Yifeng Qiu, Chris van Liempd, Bert Op het Veld, Peter G. Blanken, Chris Van Hoof:
5μW-to-10mW input power range inductive boost converter for indoor photovoltaic energy harvesting with integrated maximum power point tracking algorithm. 118-120 - Ethem Erkan Aktakka, Rebecca L. Peterson, Khalil Najafi:
A self-supplied inertial piezoelectric energy harvester with power-management IC. 120-121
Multimedia & Mobile
- Pei-Kuei Tsung, Pin-Chih Lin, Kuan-Yu Chen, Tzu-Der Chuang, Hsin-Jung Yang, Shao-Yi Chien, Li-Fu Ding, Wei-Yin Chen, Chih-Chi Cheng, Tung-Chien Chen, Liang-Gee Chen:
A 216fps 4096×2160p 3DTV set-top box SoC for free-viewpoint 3DTV applications. 124-126 - Vivienne Sze, Anantha P. Chandrakasan:
A highly parallel and scalable CABAC decoder for next generation video coding. 126-128 - Hyo-Eun Kim, Jae-Sung Yoon, Kyu-Dong Hwang, Young-Jun Kim, Jun-Seok Park, Lee-Sup Kim:
A 275mW heterogeneous multimedia processor for IC-stacking on Si-interposer. 128-130 - Jinwook Oh, Junyoung Park, Gyeonghoon Kim, Seungjin Lee, Hoi-Jun Yoo:
A 57mW embedded mixed-mode neuro-fuzzy accelerator for intelligent multi-core processor. 130-132 - Gordon Gammie, Nathan Ickes, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko:
A 28nm 0.6V low-power DSP for mobile applications. 132-134 - Gene C. H. Chuang, Pangan Ting, Jen-Yuan Hsu, Jiun-You Lai, Shun-Chang Lo, Ying-Chuan Hsiao, Tzi-Dar Chiueh:
A MIMO WiMAX SoC in 90nm CMOS for 300km/h mobility. 134-136 - Jyh-Shin Pan, Ming-Yang Chao, Eric Yeh, Wen-Wei Yang, Ching-Wen Hsueh, Shyuan Liao, Jian-Bang Lin, Shun-An Yang, Chin-Tai Liu, Tsai-Pao Lee, Jin-Ru Chen, Chia-Hua Chou, Min Chen, Den-Kai Juang, Jen-Hao Yeh, Chieh-Wei Liao, Po-Hung Chen, Kaipon Kao, Chia-Hsin Wu, Wen-Tso Huang, Shih-Hsien Liao, Chih-Heng Shih, Chien-Hsun Tung, Yen-Po Lee:
A 70Mb/s -100.5dBm sensitivity 65nm LP MIMO chipset for WiMAX portable router. 136-138 - Alan N. Willson Jr., Mukund Ojha, Shilpa Agarwal, Thriven Lai, Tzu-Chieh Kuo:
A direct digital frequency synthesizer with minimized tuning latency of 12ns. 138-140
Architectures & Circuits for Next-Generation Wireline Transceivers
- Namik Kocaman, Adesh Garg, Bharath Raghavan, Delong Cui, Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz:
11.3Gb/s CMOS SONET-compliant transceiver for both RZ and NRZ applications. 142-144 - Gaurav Chandra, Moshe Malkin:
A full-duplex 10GBase-T transmitter hybrid with SFDR >65dBc Over 1 to 400MHz in 40nm CMOS. 144-146 - Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee:
A 40Gb/s TX and RX chip set in 65nm CMOS. 146-148 - Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura:
10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. 148-150 - Satoshi Fukuda, Yasufumi Hino, Sho Ohashi, Takahiro Takeda, Satoru Shinke, Masahiro Uno, Kenji Komori, Yoshiyuki Akiyama, Kenichi Kawasaki, Ali Hajimiri:
A 12.5+12.5Gb/s full-duplex plastic waveguide interconnect. 150-152 - Rajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu:
A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS. 152-154 - Behrooz Abiri, Ravi Shivnaraine, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune:
A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS. 154-156 - Christian Menolfi, Thomas Toifl, Michael Ruegg, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Morf:
A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI. 156-158
Wireless & mm-Wave Connectivity
- Kenichi Okada, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Ning Li, Shogo Ito, Win Chaivipas, Ryo Minami, Akira Matsuzawa:
A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c. 160-162 - Alexandre Siligaris, Olivier Richard, Baudouin Martineau, Christopher Mounet, Fabrice Chaix, Romain Ferragut, Cedric Dehos, Jérôme Lantéri, Laurent Dussopt, Silas D. Yamamoto, Romain Pilard, Pierre Busson, Andreia Cathelin, Didier Belot, Pierre Vincent:
A 65nm CMOS fully integrated transceiver module for 60GHz wireless HD applications. 162-164 - Sohrab Emami, Robert F. Wiser, Ershad Ali, Mark G. Forbes, Michael Q. Gordon, Xiang Guan, Steve Lo, Patrick T. McElwee, James Parker, Jon R. Tani, Jeffrey M. Gilbert, Chinh H. Doan:
A 60GHz CMOS phased-array transceiver pair for multi-Gb/s wireless communications. 164-166 - Maryam Tabesh, Jiashu Chen, Cristian Marcu, Lingkai Kong, Shinwon Kang, Elad Alon, Ali M. Niknejad:
A 65nm CMOS 4-element Sub-34mW/element 60GHz phased-array transceiver. 166-168 - Shih-Jou Huang, Yu-Ching Yeh, Huaide Wang, Pang-Ning Chen, Jri Lee:
An 87GHz QPSK transceiver with costas-loop carrier recovery in 65nm CMOS. 168-170 - Shahram Abdollahi-Alibeik, David Weber, Hakan Dogan, William W. Si, Burcin Baytekin, Abbas Komijani, Richard Chang, Babak Vakili-Amini, MeeLan Lee, Haitao Gan, Yashar Rajavi, Hirad Samavati, Brian J. Kaczynski, Sang-Min Lee, Sotirios Limotyrakis, Hyunsik Park, Phoebe Chen, Paul Park, Mike Shuo-Wei Chen, Andrew Chang, Yangjin Oh, Jerry Jian-Ming Yang, Eric Chien-Chih Lin, Lalitkumar Nathawad, Keith Onodera, Manolis Terrovitis, Sunetra Mendis, Kai Shi, Srenik S. Mehta, Masoud Zargari, David K. Su:
A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC. 170-172 - Pui-In Mak, Rui Paulo Martins:
A 0.46mm2 4dB-NF unified receiver front-end for full-band mobile TV in 65nm CMOS. 172-174 - Hiroyuki Kobayashi, Shouhei Kousai, Yoshiaki Yoshihara, Mototsugu Hamada:
An all-digital 8-DPSK polar transmitter with second-order approximation scheme and phase rotation-constant digital PA for bluetooth EDR in 65nm CMOS. 174-176 - Jaewook Kim, Wonsik Yu, Hyun-Kyu Yu, SeongHwan Cho:
A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS. 176-178
Nyquist-Rate Converters
- Konstantinos Doris, Erwin Janssen, Claudio Nani, Athon Zanikopoulos, Gerard van der Weide:
A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist. 180-182 - Robert Payne, Charles K. Sestok, William Bright, Manar El-Chammas, Marco Corsi, David Smith, Noam Tal:
A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC. 182-184 - Jan Mulder, Frank M. L. van der Goes, Davide Vecchi, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult:
An 800MS/s dual-residue pipeline ADC in 40nm CMOS. 184-186 - Janet Brunsilius, Eric Siragusa, Steve Kosic, Frank Murden, Ege Yetis, Binh Luu, Jeff Bray, Phil Brown, Allen Barlow:
A 16b 80MS/s 100mW 77.6dB SNR CMOS pipeline ADC. 186-188 - He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. 188-190 - Marcus Yip, Anantha P. Chandrakasan:
A resolution-reconfigurable 5-to-10b 0.4-to-1V power scalable SAR ADC. 190-192 - Wei-Hsin Tseng, Chi-Wei Fan, Jieh-Tsorng Wu:
A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz. 192-194 - Yuriy M. Greshishchev, Daniel Pollex, Shing-Chi Wang, Marinette Besson, Philip Flemeke, Stefan Szilagyi, Jorge Aguirre, Chris Falt, Naim Ben-Hamida, Robert Gibbins, Peter Schvan:
A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory. 194-196
Non-Volatile Memory Solutions
- Koichi Fukuda, Yoshihisa Watanabe, Eiichi Makino, Koichi Kawakami, Jumpei Sato, Teruo Takagiwa, Naoaki Kanagawa, Hitoshi Shiga, Naoya Tokiwa, Yoshihiko Shindo, Toshiaki Edahiro, Takeshi Ogawa, Makoto Iwai, Osamu Nagao, Junji Musha, Takatoshi Minamoto, Kosuke Yanagidaira, Yuya Suzuki, Dai Nakamura, Yoshikazu Hosomura, Hiromitsu Komai, Yuka Furuta, Mai Muramoto, Rieko Tanaka, Go Shikata, Ayako Yuminaka, Kiyofumi Sakurai, Manabu Sakai, Hong Ding, Mitsuyuki Watanabe, Yosuke Kato, Toru Miwa, Alex Mak, Masaru Nakamichi, Gertjan Hemink, Dana Lee, Masaaki Higashitani, Brian Murphy, Bo Lei, Yasuhiko Matsunaga, Kiyomi Naruke, Takahiko Hara:
A 151mm2 64Gb MLC NAND flash memory in 24nm CMOS technology. 198-199 - Shyh-Shyuan Sheu, Meng-Fan Chang, Ku-Feng Lin, Che-Wei Wu, Yu-Sheng Chen, Pi-Feng Chiu, Chia-Chen Kuo, Yih-Shan Yang, Pei-Chia Chiang, Wen-Pin Lin, Che-He Lin, Heng-Yuan Lee, Peiyi Gu, Sumin Wang, Frederick T. Chen, Keng-Li Su, Chen-Hsin Lien, Kuo-Hsing Cheng, Hsin-Tun Wu, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai:
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. 200-202 - Tae-yun Kim, Sang-Don Lee, Jin-su Park, Ho-youb Cho, Byoung-sung You, Kwang-ho Baek, Jae-ho Lee, Chang-won Yang, Misun Yun, Min-su Kim, Jongwoo Kim, Eun-seong Jang, Hyun Chung, Sang-o Lim, Bong-Seok Han, Yo-Hwan Koh:
A 32Gb MLC NAND flash memory with Vth margin-expanding schemes in 26nm CMOS. 202-204 - Shuhei Tanakamaru, Chinglin Hung, Atsushi Esumi, Mitsuyoshi Ito, Kai Li, Ken Takeuchi:
95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm. 204-206 - Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Shang-Chi Wu, Chia-En Huang, Han-Chao Lai, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi:
An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory. 206-208 - Masood Qazi, Michael Clinton, Steven Bartling, Anantha P. Chandrakasan:
A low-voltage 1Mb FeRAM in 0.13μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS. 208-210 - Wataru Otsuka, Koji Miyata, Makoto Kitagawa, Keiichi Tsutsui, Tomohito Tsushima, Hiroshi Yoshihara, Tomohiro Namise, Yasuhiro Terao, Kentaro Ogata:
A 4Mb conductive-bridge resistive memory with 2.3GB/s read-throughput and 216MB/s program-throughput. 210-211 - Ki-Tae Park, Ohsuk Kwon, Sangyong Yoon, Myung-Hoon Choi, In-Mo Kim, Bo-Geun Kim, Min-Seok Kim, Yoon-Hee Choi, Seung-Hwan Shin, Youngson Song, Joo-Yong Park, Jae-Eun Lee, Chang-Gyu Eun, Ho-Chul Lee, Hyeong-Jun Kim, Jun-Hee Lee, Jong-Young Kim, Tae-Min Kweon, Hyun-Jun Yoon, Taehyun Kim, Dong-Kyo Shim, Jongsun Sel, Ji-Yeon Shin, Pansuk Kwak, Jin-Man Han, Keon-Soo Kim, Sungsoo Lee, Youngho Lim, Tae-Sung Jung:
A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology. 212-213
Design in Emerging Technologies
- Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai:
A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme. 216-218 - Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
100V AC power meter system-on-a-film (SoF) integrating 20V organic CMOS digital and analog circuits with floating gate for process-variation compensation and 100V organic PMOS rectifier. 218-220 - Shingo Takahashi, Nobuhide Yoshida, Kenichi Maruhashi, Muneo Fukaishi:
Real-time current-waveform sensor with plugless energy harvesting from AC power lines for home/building energy-management systems. 220-222 - Alexander V. Rylyakov, Clint Schow, Benjamin G. Lee, William M. J. Green, Joris Van Campenhout, Min Yang, Fuad E. Doany, Solomon Assefa, Christopher V. Jahnes, Jeffrey A. Kash, Yurii A. Vlasov:
A 3.9ns 8.9mW 4×4 silicon photonic switch hybrid integrated with CMOS driver. 222-224 - Erik Öjefors, Janus Grzyb, Yan Zhao, Bernd Heinemann, Bernd Tillack, Ullrich R. Pfeiffer:
A 820GHz SiGe chipset for terahertz active imaging applications. 224-226 - Hiroaki Ishihara, Toshiyuki Umeda, Katsuya Ohno, Shigeyasu Iwata, Fumi Moritsuka, Tetsuro Itakura, Manabu Ishibe, Keijiro Hijikata, Yasunori Maki:
A 130μA wake-up receiver SoC in 0.13μm CMOS for reducing standby power of an electric appliance controlled by an infrared remote controller. 226-228 - Makoto Miyamura, Shogo Nakaya, Munehiro Tada, Toshitsugu Sakamoto, Koichiro Okamoto, Naoki Banno, Shinji Ishida, Kimihiko Ito, Hiromitsu Hada, Noboru Sakimura, Tadahiko Sugibayashi, Masato Motomura:
Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS. 228-229 - Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda:
6W/25mm2 inductive power transfer for non-contact wafer-level testing. 230-232 - Mariya Kurchuk, Colin Weltin-Wu, Dominique Morche, Yannis P. Tsividis:
GHz-range continuous-time programmable digital FIR with power dissipation that automatically adapts to signal activity. 232-234
Analog Techniques
- Jong Tae Hwang, Kunhee Cho, Donghwan Kim, Minho Jung, Gyehyun Cho, Seunguk Yang:
A simple LED lamp driver IC with intelligent power-factor correction. 236-238 - Sachin Rao, Qadeer Khan, Sarvesh Bang, Damian Swank, Arun Rao, William McIntyre, Pavan Kumar Hanumolu:
A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing. 238-240 - Mykhaylo A. Teplechuk, Tony Gribben, Christophe Amadi:
Filterless integrated class-D audio amplifier achieving 0.0012% THD+N and 96dB PSRR when supplying 1.2W. 240-242 - Yoshinori Kusuda:
A 5.9nV/√Hz chopper operational amplifier with 0.78μV maximum offset and 28.3nV/°C offset drift. 242-244 - Rong Wu, Johan H. Huijsing, Kofi A. A. Makinwa:
A current-feedback instrumentation amplifier with a gain error reduction loop and 0.06% untrimmed gain error. 244-246 - Chinwuba D. Ezekwe, Johan P. Vanderhaegen, Xinyu Xing, Ganesh K. Balachandran:
A 6.7nV/√Hz Sub-mHz-1/f-corner 14b analog-to-digital interface for rail-to-rail precision voltage sensing. 246-248 - Martijn F. Snoeij, Mikhail V. Ivanov:
A 36V JFET-input bipolar operational amplifier with 1μV/°C maximum offset drift and -126dB total harmonic distortion. 248-250 - Gwilym F. Luff:
13.8A 3.3V-supply 120mW differential ADC driver amplifier in 0.18μm SiGe BiCMOS with 108dBc IM3 at 100MHz. 250-252
High-Performance Embedded Memory
- Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens:
A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements. 254-256 - Gary S. Ditlow, Robert K. Montoye, Salvatore N. Storino, Sherman M. Dance, Sebastian Ehrenreich, Bruce M. Fleischer, Thomas W. Fox, Kyle M. Holmes, Junichi Mihara, Yutaka Nakamura, Shohji Onishi, Robert Shearer, Dieter F. Wendel, Leland Chang:
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. 256-258 - Don Weiss, Michael Dreesen, Michael Ciraula, Carson Henrion, Chris Helt, Ryan Freese, Tommy Miles, Anita Karegar, Russell Schreiber, Bryan Schneller, John J. Wuu:
An 8MB level-3 cache in 32nm SOI with column-select aliasing. 258-260