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ORCIDIEEE Journal of Solid-State Circuits, Volume 46
Volume 46, Number 1, January 2011
- Christoph Studer, Christian Benkeser, Sandro Belfanti, Qiuting Huang:
Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE. 8-17 - David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw:
A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation. 18-31 - Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki:
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. 32-41 - Seungjin Lee, Jinwook Oh, Junyoung Park, Joonsoo Kwon, Minsu Kim, Hoi-Jun Yoo:
A 345 mW Heterogeneous Many-Core Processor With an Intelligent Inference Engine for Robust Object Recognition. 42-51 - Guido De Sandre, Luca Bettini, Alessandro Pirola, Lionel Marmonier, Marco Pasotti, Massimo Borghi, Paolo Mattavelli
, Paola Zuliani, Luca Scotti, Gianfranco Mastracchio, Ferdinando Bedeschi, Roberto Gastaldi, Roberto Bez:
A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology. 52-63 - John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Cao:
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. 64-75 - Pramod Kolar, Eric Karl, Uddalak Bhattacharya, Fatih Hamzaoglu, Henry Nho, Yong-Gee Ng, Yih Wang, Kevin Zhang:
A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation. 76-84 - Masood Qazi, Kevin Stawiasz, Leland Chang, Anantha P. Chandrakasan:
A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS. 85-96 - Changhyuk Lee, Sok-Kyu Lee, Sunghoon Ahn, Jinhaeng Lee, Wonsun Park, Yongdeok Cho, Chaekyu Jang, Chulwoo Yang, Sanghwa Chung, In-Suk Yun, Byoungin Joo, Byoungkwan Jeong, Jeeyul Kim, Jeakwan Kwon, Hyunjong Jin, Yujong Noh, Jooyun Ha, Moonsoo Sung, Daeil Choi, Sanghwan Kim, Jeawon Choi, Taeho Jeon, Heejoung Park, Joong-Seob Yang, Yo-Hwan Koh:
A 32-Gb MLC NAND Flash Memory With Vth Endurance Enhancing Schemes in 32 nm CMOS. 97-106 - Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seokwon Hwang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun:
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction. 107-118 - Nasser A. Kurd, Subramani Bhamidipati, Christopher Mozak, Jeffrey L. Miller, Praveen Mosalikanti, Timothy M. Wilson, Ali M. El-Husseini, Mark Neidengard, Ramy E. Aly, Mahadev Nemani, Muntaquim Chowdhury, Rajesh Kumar:
A Family of 32 nm IA Processors. 119-130 - Jinuk Luke Shin, Dawei Huang, Bruce Petrick, Changku Hwang, Kenway W. Tam, Alan P. Smith, Ha Pham, Hongping Penny Li, Timothy Johnson, Francis Schumacher, Ana Sonia Leon, Allan Strong:
A 40 nm 16-Core 128-Thread SPARC SoC Processor. 131-144 - Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban:
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. 145-161 - Ravi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, Amy Novak, Sam Naffziger:
An x86-64 Core in 32 nm SOI CMOS. 162-172 - Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart:
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. 173-183 - Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar:
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. 184-193 - Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De:
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. 194-208 - Refet Firat Yazicioglu, Sunyoung Kim, Tom Torfs, Hyejung Kim, Chris Van Hoof:
A 30 μ W Analog Signal Processor ASIC for Portable Biopotential Signal Monitoring. 209-223 - Hossein Miri Lavasani, Wanling Pan, Brandon Harrington, Reza Abdolvand, Farrokh Ayazi:
A 76 dB Ω 1.7 GHz 0.18 μ m CMOS Tunable TIA Using Broadband Current Pre-Amplifier for High Frequency Lateral MEMS Oscillators. 224-235 - Youngcheol Chae, Jimin Cheon, Seunghyun Lim, Minho Kwon, Kwisung Yoo, Wunki Jung, Dong-Hun Lee, Seogheon Ham, Gunhee Han:
A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel Delta Sigma ADC Architecture. 236-247 - David Stoppa, Nicola Massari, Lucio Pancheri, Mattia Malfatti, Matteo Perenzoni, Lorenzo Gonzo:
A Range Image Sensor Based on 10-μm Lock-In Pixels in 0.18-μm CMOS Imaging Technology. 248-258 - Christoph Posch, Daniel Matolin, Rainer Wohlgenannt:
A QVGA 143 dB Dynamic Range Frame-Free PWM Image Sensor With Lossless Pixel-Level Video Compression and Time-Domain CDS. 259-275 - Hagen Marien, Michiel Steyaert, Erik van Veenendaal, Paul Heremans:
A Fully Integrated Delta Sigma ADC in Organic Thin-Film Transistor Technology on Flexible Plastic Foil. 276-284 - Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects. 285-292 - Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal:
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. 293-307 - Matthew Spencer, Fred Chen, Cheng C. Wang, Rhesa Nathanael, Hossein Fariborzi, Abhinav Gupta, Hei Kam, Vincent Pott, Jaeseok Jeon, Tsu-Jae King Liu, Dejan Markovic, Elad Alon, Vladimir Stojanovic:
Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications. 308-320 - Kunal Paralikar, Peng Cong, Ofer Yizhar, Lief Ericsson Fenno, Wesley Santa, Chris Nielsen, David Dinsmoor, Bob Hocken, Gordon Munns, Jon Giftakis, Karl Deisseroth, Timothy Denison:
An Implantable Optical Stimulation Delivery System for Actuating an Excitable Biosubstrate. 321-332 - Yogesh K. Ramadass, Anantha P. Chandrakasan:
A Battery-Less Thermoelectric Energy Harvesting Interface Circuit With 35 mV Startup Voltage. 333-341 - Nan Sun, Tae-Jong Yoon, Hakho Lee, William F. Andress, Ralph Weissleder, Donhee Ham:
Palm NMR and 1-Chip NMR. 342-352 - Long Yan, Joonsung Bae, Seulki Lee, Taehwan Roh, Kiseok Song, Hoi-Jun Yoo:
A 3.9 mW 25-Electrode Reconfigured Sensor for Wearable Cardiac Monitoring System. 353-364
Volume 46, Number 2, February 2011
- Wuttichai Lerdsitsomboon, Kenneth K. O:
Technique for Integration of a Wireless Switch in a 2.4 GHz Single Chip Radio. 368-377 - Lei Zhou, Chun-Cheng Wang, Zhiming Chen, Payam Heydari:
A W-band CMOS Receiver Chipset for Millimeter-Wave Radiometer Systems. 378-391 - Deyi Pi, Byung-Kwan Chun, Payam Heydari:
A Synthesis-Based Bandwidth Enhancement Technique for CMOS Amplifiers: Theory and Design. 392-402 - Imran Bashir, Robert Bogdan Staszewski, Oren E. Eliezer, Bhaskar Banerjee, Poras T. Balsara:
A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter. 403-415 - Qiang Zhu, Yang Xu:
A 228 μ W 750 MHz BPSK Demodulator Based on Injection Locking. 416-423 - Heesoo Song, Deok-Soo Kim, Do-Hwan Oh, Suhwan Kim, Deog-Kyoon Jeong:
A 1.0-4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control. 424-434 - Young-Sang Kim, Seon-Kyoo Lee, Hong-June Park, Jae-Yoon Sim:
A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL. 435-444 - Xiaohong Peng, Willy Sansen, Ligang Hou, Jinhui Wang, Wuchen Wu:
Impedance Adapting Compensation for Low-Power Multistage Amplifiers. 445-451 - Song Guo, Hoi Lee:
Dual Active-Capacitive-Feedback Compensation for Low-Power Large-Capacitive-Load Three-Stage Amplifiers. 452-464 - Luca Magnelli, Felice Crupi, Pasquale Corsonello, Calogero Pace, Giuseppe Iannaccone:
A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference. 465-474 - Johan Borg, Jonny Johansson:
An Ultrasonic Transducer Interface IC With Integrated Push-Pull 40 Vpp, 400 mA Current Output, 8-bit DAC and Integrated HV Multiplexer. 475-484 - Yashodhan Moghe, Torsten Lehmann, Tim Piessens:
Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 μ m HV-CMOS Technology. 485-497 - Eleonora Franchi Scarselli, Antonio Gnudi, Federico Natali, Mauro Scandiuzzo, Roberto Canegallo, Roberto Guerrieri:
Automatic Compensation of the Voltage Attenuation in 3-D Interconnection Based on Capacitive Coupling. 498-506 - Po-Tsang Huang, Wei Hwang:
A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables. 507-519 - Meng-Fan Chang, Shi-Wei Chang, Po-Wei Chou, Wei-Cheng Wu:
A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications. 520-529 - Daisaburo Takashima, Yasushi Nagadomi, Kosuke Hatsuda, Yohji Watanabe, Shuso Fujii:
A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance. 530-536 - Ming-Dou Ker, Wen-Yi Chen, Wuu-Trong Shieh, I-Ju Wei:
Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs. 537-545 - Alberto Pirola, Antonio Liscidini, Rinaldo Castello:
Corrections to "Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping" [Sep 10 1770-1780]. 546
Volume 46, Number 3, March 2011
- Federico Vecchi, Stefano Bozzola, Enrico Temporiti, Davide Guermandi, Massimo Pozzoni, Matteo Repossi, Marco Cusmai, Ugo Decanis, Andrea Mazzanti, Francesco Svelto:
A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS. 551-561 - Desheng Ma, Fa Foster Dai, Richard C. Jaeger, J. David Irwin:
An X- and Ku-Band Wideband Recursive Receiver MMIC With Gain-Reuse. 562-571 - Masaki Kitsunezuka, Takashi Tokairin, Tadashi Maeda, Muneo Fukaishi:
A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme. 572-582 - Omeed Momeni, Ehsan Afshari:
High Power Terahertz and Millimeter-Wave Oscillator Design: A Systematic Approach. 583-597 - Shih-An Yu, Yves Baeyens, Joseph Weiner, Ut-Va Koc, Marta Rambaud, Fang-Ren Liao, Young-Kai Chen, Peter R. Kinget:
A Single-Chip 125-MHz to 32-GHz Signal Source in 0.18- μ m SiGe BiCMOS. 598-614 - Pin-En Su, Sudhakar Pamarti:
A 2.4 GHz Wideband Open-Loop GFSK Transmitter With Phase Quantization Noise Cancellation. 615-626 - Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation. 627-638 - Vijay Dhanasekaran, Manisha Gambhir, Mohamed M. Elsayed, Edgar Sánchez-Sinencio, José Silva-Martínez, Chinmaya Mishra, Lei Chen, Erik Pankratz:
A Continuous Time Multi-Bit Delta Sigma ADC Using Time Domain Quantizer and Feedback Element. 639-650 - Seon-Kyoo Lee, Seung-Jin Park, Hong-June Park, Jae-Yoon Sim:
A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface. 651-659 - Mohammad Taherzadeh-Sani, Anas A. Hamoui:
A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS. 660-668 - Jorge Fernández-Berni, Ricardo Carmona-Galán, Luis Carranza-González:
FLIP-Q: A QCIF Resolution Focal-Plane Array for Low-Power Image Processing. 669-680 - Daisaburo Takashima, Yasushi Nagadomi, Tohru Ozaki:
A 100 MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) Cell. 681-689 - Myoung Jin Lee:
A Sensing Noise Compensation Bit Line Sense Amplifier for Low Voltage Applications. 690-694 - Cheng-Hung Lo, Shi-Yu Huang:
P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation. 695-704 - David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw:
Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation". 705
Volume 46, Number 4, April 2011
- Srinivasa R. Sridhara, Michael DiRenzo, Srinivas Lingam, Seok-Jun Lee, Ra Blazquez, Jay Maxey, Samer Ghanem, Yu-Hung Lee, Rami A. Abdallah, Prashant Singh, Manish Goel:
Microwatt Embedded Processor Platform for Medical System-on-Chip Applications. 721-730 - Meysam Azin, David J. Guggenmos, Scott Barbay, Randolph J. Nudo, Pedram Mohseni:
A Battery-Powered Activity-Dependent Intracortical Microstimulation IC for Brain-Machine-Brain Interface. 731-745 - Jose L. Bohorquez, Marcus Yip, Anantha P. Chandrakasan, Joel L. Dawson:
A Biomedical Sensor Interface With a sinc Filter and Interference Cancellation. 746-756 - Praveen Salihundam, Shailendra Jain, Tiju Jacob, Shasi Kumar, Vasantha Erraguntla, Yatin Vasant Hoskote, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar:
A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS. 757-766 - Sanu Mathew, Farhana Sheikh, Michael E. Kounavis, Shay Gueron, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark A. Anders, Ram Krishnamurthy:
53 Gbps Native GF(2 4) 2 Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors. 767-776 - Dajiang Zhou, Jinjia Zhou, Xun He, Jiayi Zhu, Ji Kong, Peilin Liu, Satoshi Goto:
A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip. 777-788 - Takushi Hashida, Makoto Nagata:
An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration. 789-796 - Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De:
Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. 797-805 - Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi:
Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs. 806-814 - Jui-Jen Wu, Yen-Hui Chen, Meng-Fan Chang, Po-Wei Chou, Chien-Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi:
A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme. 815-827 - Tomonori Sekiguchi, Kazuo Ono, Akira Kotabe, Yoshimitsu Yanagawa:
1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing. 828-837 - Manar El-Chammas, Boris Murmann:
A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration. 838-847 - Chun-Cheng Huang, Chung-Yi Wang, Jieh-Tsorng Wu:
A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques. 848-858 - Chun C. Lee, Michael P. Flynn:
A SAR-Assisted Two-Stage Pipeline ADC. 859-869 - Hooman Darabi, Paul Chang, Henrik Jensen, Alireza Zolfaghari, Paul Lettieri, John C. Leete, Behnam Mohammadi, Janice Chiu, Qiang (Tom) Li, Shr-Lung Chen, Zhimin Zhou, Morteza Vadipour, C. Chen, Yuyu Chang, Ahmad Mirzaei, Ahmad Yazdi, Mohammad Nariman, Amir Hadji-Abdolhamid, Ethan Chang, Barry Zhao, Kevin Juan, Puneet Suri, Claire Guan, Louie Serrano, John Leung, J. Shin, Jay Kim, Huey Tran, Patrick Kilcoyne, H. Vinh, Eric Raith, M. Koscal, Ajat Hukkoo, C. Hayek, V. Rakhshani, Charlie Wilcoxson, Maryam Rofougaran, Ahmadreza Rofougaran:
A Quad-Band GSM/GPRS/EDGE SoC in 65 nm CMOS. 870-882 - Akira Tanabe, Ken'ichiro Hijioka, Hirokazu Nagase, Yoshihiro Hayashi:
A Novel Variable Inductor Using a Bridge Circuit and Its Application to a 5-20 GHz Tunable LC-VCO. 883-893 - Behzad Razavi:
A 300-GHz Fundamental Oscillator in 65-nm CMOS Technology. 894-903 - Yu-Huei Lee, Yao-Yi Yang, Shih-Jung Wang, Ke-Horng Chen, Ying-Hsi Lin, Yi-Kuang Chen, Chen-Chih Huang:
Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters With 91% Peak Efficiency. 904-915 - Michaël Pelissier, Joni Jantunen, Bertrand Gomez, Jarmo Arponen, Gilles Masson, Serigne Dia, Jaakko Varteva, Marjorie Gary:
A 112 Mb/s Full Duplex Remotely-Powered Impulse-UWB RFID Transceiver for Wireless NV-Memory Applications. 916-927 - Joonsung Bae, Long Yan, Hoi-Jun Yoo:
A Low Energy Injection-Locked FSK Transceiver With Frequency-to-Amplitude Conversion for Body Sensor Applications. 928-937 - Adam C. Heiberg, Thomas William Brown, Terri S. Fiez, Kartikeya Mayaram:
A 250 mV, 352 μ W GPS Receiver RF Front-End in 130 nm CMOS. 938-949 - Ahmad Mirzaei, Hooman Darabi, Ahmad Yazdi, Zhimin Zhou, Ethan Chang, Puneet Suri:
A 65 nm CMOS Quad-Band SAW-Less Receiver SoC for GSM/GPRS/EDGE. 950-964 - Noriyuki Miura, Tsunaaki Shidei, Yuxiang Yuan, Shusuke Kawai, Keita Takatsu, Yuji Kiyota, Yuichi Asano, Tadahiro Kuroda:
A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme. 965-973 - Jared Zerbe, Barry Daly, Lei Luo, Bill Stonecypher, Wayne D. Dettloff, John C. Eble, Teva Stone, Jihong Ren, Brian S. Leibowitz, Michael Bucher, Patrick Satarzadeh, Qi Lin, Yue Lu, Ravi T. Kollipara:
A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques. 974-985 - Tsuyoshi Ebuchi, Yoshihide Komatsu, Masatomo Miura, Tomoko Chiba, Toru Iwata, Shiro Dosho, Takefumi Yoshikawa:
An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration. 986-991
Volume 46, Number 5, May 2011
- Amir Ghaffari, Eric A. M. Klumperink, Michiel C. M. Soer, Bram Nauta:
Tunable High-Q N-Path Band-Pass Filters: Modeling and Verification. 998-1010 - Shahriar Shahramian, Adam Hart, Alexander Tomkins, Anthony Chan Carusone, Patrice Garcia, Pascal Chevalier, Sorin P. Voinigescu:
Design of a Dual W- and D-Band PLL. 1011-1022 - Yan-Yu Huang, Wangmyong Woo, Youngchang Yoon, Chang-Ho Lee:
Highly Linear RF CMOS Variable Attenuators With Adaptive Body Biasing. 1023-1033 - Jihwan Kim, Youngchang Yoon, Hyungwook Kim, Kyu Hwan An, Woonyun Kim, Hyun-Woong Kim, Chang-Ho Lee, Kevin T. Kornegay:
A Linear Multi-Mode CMOS Power Amplifier With Discrete Resizing and Concurrent Power Combining Structure. 1034-1048 - Jagdish Nayayan Pandey, Brian P. Otis:
A Sub-100 μ W MICS/ISM Band Transmitter Based on Injection-Locking and Frequency Multiplication. 1049-1058 - Arun Natarajan, Scott K. Reynolds, Ming-Da Tsai, Sean T. Nicolson, Jing-Hong Conan Zhan, Dong Gun Kam, Duixian Liu, Yen-Lin Oscar Huang, Alberto Valdes-Garcia, Brian A. Floyd:
A Fully-Integrated 16-Element Phased-Array Receiver in SiGe BiCMOS for 60-GHz Communications. 1059-1075 - Changhui Hu, Rahul Khanna, Jay J. Nejedlo, Kangmin Hu, Huaping Liu, Patrick Yin Chiang:
A 90 nm-CMOS, 500 Mbps, 3-5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization. 1076-1088 - James P. Roach, Lee-Wen Chen, Peter Clarke, Amit Dikshit, Francis M. Rotella:
Key Aspects in Modeling of Thin Epi SOS Technology With Application of BSIMSOI. 1089-1099 - Jian Liu, Xin Wang, Hui Zhao, Qiang Fang, Albert Z. Wang, Lin Lin, He Tang, Siqiang Fan, Bin Zhao, Shi-Jie Wen, Richard Wong:
Design and Analysis of Low-Voltage Low-Parasitic ESD Protection for RF ICs in CMOS. 1100-1110 - Mohamed El-Nozahi, Ahmed A. Helmy, Edgar Sánchez-Sinencio, Kamran Entesari:
An Inductor-Less Noise-Cancelling Broadband Low Noise Amplifier With Composite Transistor Pair in 90 nm CMOS Technology. 1111-1122 - Joohwa Kim, James F. Buckwalter:
Staggered Gain for 100+ GHz Broadband Amplifiers. 1123-1136 - Christian Knochenhauer, Christoph Scheytt, Frank Ellinger:
A Compact, Low-Power 40-GBit/s Modulator Driver With 6-V Differential Output Swing in 0.25- μ m SiGe BiCMOS. 1137-1146 - Youngmin Park, David D. Wentzloff:
An All-Digital 12 pJ/Pulse IR-UWB Transmitter Synthesized From a Standard Cell Library. 1147-1157 - Shih-Hao Huang, Wei-Zen Chen, Yu-Wei Chang, Yang-Tung Huang:
A 10-Gb/s OEIC with Meshed Spatially-Modulated Photo Detector in 0.18-μm CMOS Technology. 1158-1169 - Niksa Tadic, Milena Zogovic, Wolfgang Gaberl, Horst Zimmermann:
A 78.4 dB Photo-Sensitivity Dynamic Range, 285 T Ω Hz Transimpedance Bandwidth Product BiCMOS Optical Sensor for Optical Storage Systems. 1170-1182 - Sanquan Song, Vladimir Stojanovic:
A 6.25 Gb/s Voltage-Time Conversion Based Fractionally Spaced Linear Receive Equalizer for Mesochronous High-Speed Links. 1183-1197 - Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang:
A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique. 1198-1213 - Vaibhav Karkare, Sarah Gibson, Dejan Markovic:
A 130- μ W, 64-Channel Neural Spike-Sorting DSP Chip. 1214-1222