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ORCIDManuel A. d'Abreu
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2010 – 2019
- 2011
[c23]Manuel A. d'Abreu:
Nand Flash Memory - Product Trends, Technology Overview, and Technical Challenges. Asian Test Symposium 2011: 463
2000 – 2009
- 2009
- [c22]Bhanu Kapoor, Shankar Hemmady, Shireesh Verma, Kaushik Roy, Manuel A. d'Abreu:
Impact of SoC power management techniques on verification and testing. ISQED 2009: 692-695 - 2008
- [j4]Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu:
Controllability of Static CMOS Circuits for Timing Characterization. J. Electron. Test. 24(5): 481-496 (2008) - [c21]Bhanu Kapoor, John Goodenough, Shankar Hemmady, Shireesh Verma, Manuel A. d'Abreu, Kaushik Roy:
Panel: SoC power management implications on validation and testing. HLDVT 2008: 135-137 - 2004
- [c20]Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu:
Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing. ITC 2004: 1118-1127 - 2002
- [c19]Manuel A. d'Abreu:
Noise-Its Sources, and Impact on Design and Test of Mixed Signal Circuits. DELTA 2002: 370-376 - 2000
- [c18]Manuel A. d'Abreu:
Manufacturing and Test Considerations in System-On-Chip Designs. VLSI Design 2000: 176-177
1990 – 1999
- 1999
- [c17]Rathish Jayabharathi, Manuel A. d'Abreu, Jacob A. Abraham:
FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model. VLSI Design 1999: 232-235 - 1996
- [c16]Prakash Arunachalam, Jacob A. Abraham, Manuel A. d'Abreu:
A Hierarchal Approach for Power Reduction in VLSI Chips. Great Lakes Symposium on VLSI 1996: 182- - [c15]Sankaran Karthik, Mark Aitken, Glidden Martin, Srinivasu Pappula, Bob Stettler, Praveen Vishakantaiah, Manuel A. d'Abreu, Jacob A. Abraham:
Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor. ITC 1996: 160-166 - 1994
- [c14]Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther:
Microprocessor Testing: Which Technique is Best? (Panel). DAC 1994: 294 - 1993
- [j3]Abhijit Chatterjee, Manuel A. d'Abreu:
The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques. IEEE Trans. Computers 42(7): 794-808 (1993) - [j2]Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu:
Greedy hardware optimization for linear digital circuits using number splitting and refactorization. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 423-431 (1993) - [c13]Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu:
Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting. VLSI Design 1993: 154-159 - 1992
- [c12]Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu:
Automatic test generation for linear digital systems with bi-level search using matrix transform methods. ICCAD 1992: 224-228 - [c11]Rabindra K. Roy, Naveena Nagi, Abhijit Chatterjee, Manuel A. d'Abreu:
Delay fault testing of iterative arithmetic arrays. VTS 1992: 25-30 - 1991
- [c10]Abhijit Chatterjee, Manuel A. d'Abreu:
Concurrent Error Detection and Fault-Tolerance in Linear Digital State Variable Systems. FTCS 1991: 136-143 - [c9]Abhijit Chatterjee, Manuel A. d'Abreu:
Syndrome-Based Functional Delay Fault Location in Linear Digital Data-Flow Graphs. ICCD 1991: 212-215
1980 – 1989
- 1989
- [j1]Albert E. Casavant, Manuel A. d'Abreu, Martin Dragomirecky, David A. Duff, Jeffrey R. Jasica, Michael J. Hartman, Ki Soo Hwang, William D. Smith:
A synthesis environment for designing DSP systems. IEEE Des. Test 6(2): 35-44 (1989) - [c8]William D. Smith, David A. Duff, Martin Dragomirecky, James L. Caldwell
, Michael J. Hartman, Jeffrey R. Jasica, Manuel A. d'Abreu:
FACE Core Environment: The Model and Its Application in CAE/CAD Tool Development. DAC 1989: 466-471 - [c7]Martin Dragomirecky, Ephraim P. Glinert, Jeffrey R. Jasica, David A. Duff, William D. Smith, Manuel A. d'Abreu:
High-Level Graphical User Interface Management in the FACE Synthesis Environment. DAC 1989: 549-554 - [c6]Ki Soo Hwang, Albert E. Casavant, Ching-Tang Chang, Manuel A. d'Abreu:
Scheduling and hardware sharing in pipelined data paths. ICCAD 1989: 24-27 - 1988
- [c5]E. Berkcan, Manuel A. d'Abreu, W. Laughton:
Analog Compilation Based on Successive Decompositions. DAC 1988: 369-375 - [c4]Ki Soo Hwang, Albert E. Casavant, Martin Dragomirecky, Manuel A. d'Abreu:
Constrained conditional resource sharing in pipeline synthesis. ICCAD 1988: 52-55 - [c3]William D. Smith, Jeffrey R. Jasica, Michael J. Hartman, Manuel A. d'Abreu:
Flexible module generation in the FACE design environment. ICCAD 1988: 396-399 - 1984
- [c2]Manuel A. d'Abreu, K. L. Cheong, C. T. Flanagan:
Oracle - a simulator for Bipolar and MOS IC design. DAC 1984: 343-349 - 1980
- [c1]Manuel A. d'Abreu, Edward W. Thompson:
An accurate functional level concurrent fault simulator. DAC 1980: 210-217
Coauthor Index
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